RM0008 Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 12 1031/1096
EHERNET DMA receive poll demand register (ETH_DMARPDR)
Address offset: 0x1008
Reset value: 0x0000 0000
This register is used by the application to instruct the DMA to poll the receive descriptor list.
The Receive poll demand register enables the receive DMA to check for new descriptors.
This command is given to wake up the RxDMA from Suspend state. The RxDMA can go into
Suspend state only due to the unavailability of descriptors owned by it.
Ethernet DMA receive descriptor list address register (ETH_DMARDLAR)
Address offset: 0x100C
Reset value: 0x0000 0000
The Receive descriptor list address register points to the start of the receive descriptor list.
The descriptor lists reside in the STM32F107xx's physical memory space and must be
word-aligned. The DMA internally converts it to bus-width aligned address by making the
corresponding LS bits low. Writing to the ETH_DMARDLAR register is permitted only when
reception is stopped. When stopped, the ETH_DMARDLAR register must be written to
before the receive Start command is given.
Ethernet DMA transmit descriptor list address register (ETH_DMATDLAR)
Address offset: 0x1010
Reset value: 0x0000 0000
The Transmit descriptor list address register points to the start of the transmit descriptor list.
The descriptor lists reside in the STM32F107xx's physical memory space and must be
word-aligned. The DMA internally converts it to bus-width-aligned address by taking the
corresponding LSB to low. Writing to the ETH_DMATDLAR register is permitted only when
313029282726252423222120191817161514131211109876543210
RPD
rw_wt
Bits 31:0 RPD: Receive poll demand
When these bits are written with any value, the DMA reads the current descriptor pointed to by
the ETH_DMACHRDR register. If that descriptor is not available (owned by Host), reception
returns to the Suspended state and ETH_DMASR register bit 7 is not asserted. If the
descriptor is available, the Receive DMA returns to active state.
313029282726252423222120191817161514131211109876543210
SRL
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 SRL: Start of receive list
This field contains the base address of the first descriptor in the receive descriptor list. The
LSB bits [1/2/3:0] for 32/64/128-bit bus width) are internally ignored and taken as all-zero by
the DMA. Hence these LSB bits are read only.
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