Ethernet (ETH): media access control (MAC) with DMA controller RM0008
1030/1096 Doc ID 13902 Rev 12
Ethernet DMA transmit poll demand register (ETH_DMATPDR)
Address offset: 0x1004
Reset value: 0x0000 0000
This register is used by the application to instruct the DMA to poll the transmit descriptor list.
The transmit poll demand register enables the Transmit DMA to check whether or not the
current descriptor is owned by DMA. The Transmit Poll Demand command is given to wake
up the TxDMA if it is in Suspend mode. The TxDMA can go into Suspend mode due to an
underflow error in a transmitted frame or due to the unavailability of descriptors owned by
transmit DMA. You can issue this command anytime and the TxDMA resets it once it starts
re-fetching the current descriptor from host memory.
Bits 13:8 PBL: Programmable burst length
These bits indicate the maximum number of beats to be transferred in one DMA transaction.
This is the maximum value that is used in a single block read/write operation. The DMA always
attempts to burst as specified in PBL each time it starts a burst transfer on the host bus. PBL
can be programmed with permissible values of 1, 2, 4, 8, 16, and 32. Any other value results in
undefined behavior. When USP is set, this PBL value is applicable for TxDMA transactions
only.
The PBL values have the following limitations:
– The maximum number of beats (PBL) possible is limited by the size of the Tx FIFO and Rx
FIFO.
– The FIFO has a constraint that the maximum beat supported is half the depth of the FIFO.
– If the PBL is common for both transmit and receive DMA, the minimum Rx FIFO and Tx
FIFO depths must be considered.
– Do not program out-of-range PBL values, because the system may not behave properly.
Bit 7 Reserved
Bits 6:2 DSL: Descriptor skip length
This bit specifies the number of words to skip between two unchained descriptors. The
address skipping starts from the end of current descriptor to the start of next descriptor. When
DSL value equals zero, the descriptor table is taken as contiguous by the DMA, in Ring mode.
Bit 1 DA: DMA Arbitration
0: Round-robin with Rx:Tx priority given in bits [15:14]
1: Rx has priority over Tx
Bit 0 SR: Software reset
When this bit is set, the MAC DMA controller resets all MAC Subsystem internal registers and
logic. It is cleared automatically after the reset operation has completed in all of the core clock
domains. Read a 0 value in this bit before re-programming any register of the core.
313029282726252423222120191817161514131211109876543210
TPD
rw_wt
Bits 31:0 TPD: Transmit poll demand
When these bits are written with any value, the DMA reads the current descriptor pointed to by
the ETH_DMACHTDR register. If that descriptor is not available (owned by Host), transmission
returns to the Suspend state and ETH_DMASR register bit 2 is asserted. If the descriptor is
available, transmission resumes.
To Next Page
Loading...
Need help?
General
