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Ethernet (ETH): media access control (MAC) with DMA controller RM0008

1040/1096 Doc ID 13902 Rev 12

Ethernet DMA missed frame and buffer overflow counter register

(ETH_DMAMFBOCR)

Address offset: 0x1020

Reset value: 0x0000 0000

The DMA maintains two counters to track the number of missed frames during reception.

This register reports the current value of the counter. The counter is used for diagnostic

purposes. Bits [15:0] indicate missed frames due to the STM32F107xx buffer being

unavailable (no receive descriptor was available). Bits [27:17] indicate missed frames due to

Rx FIFO overflow conditions and runt frames (good frames of less than 64 bytes).

Ethernet DMA current host transmit descriptor register (ETH_DMACHTDR)

Address offset: 0x1048

Reset value: 0x0000 0000

The Current host transmit descriptor register points to the start address of the current

transmit descriptor read by the DMA.

313029282726252423222120191817161514131211109876543210

Reserved

OFOC

MFA

OMFC

MFC

rc_

Bits 31:29 Reserved

Bit 28 OFOC: Overflow bit for FIFO overflow counter

Bits 27:17 MFA: Missed frames by the application

Indicates the number of frames missed by the application

Bit 16 OMFC: Overflow bit for missed frame counter

Bits 15:0 MFC: Missed frames by the controller

Indicates the number of frames missed by the Controller due to the host receive buffer being

unavailable. This counter is incremented each time the DMA discards an incoming frame.

313029282726252423222120191817161514131211109876543210

HTDAP

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Bits 31:0 HTDAP: Host transmit descriptor address pointer

Cleared on reset. Pointer updated by DMA during operation.

ST STM32F101xx User Manual

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