RM0008 Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 12 1041/1096
Ethernet DMA current host receive descriptor register (ETH_DMACHRDR)
Address offset: 0x104C
Reset value: 0x0000 0000
The Current host receive descriptor register points to the start address of the current receive
descriptor read by the DMA.
Ethernet DMA current host transmit buffer address register
(ETH_DMACHTBAR)
Address offset: 0x1050
Reset value: 0x0000 0000
The Current host transmit buffer address register points to the current transmit buffer
address being read by the DMA.
Ethernet DMA current host receive buffer address register
(ETH_DMACHRBAR)
Address offset: 0x1054
Reset value: 0x0000 0000
The current host receive buffer address register points to the current receive buffer address
being read by the DMA.
313029282726252423222120191817161514131211109876543210
HRDAP
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr
Bits 31:0 HRDAP: Host receive descriptor address pointer
Cleared on Reset. Pointer updated by DMA during operation.
313029282726252423222120191817161514131211109876543210
HTBAP
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr
Bits 31:0 HTBAP: Host transmit buffer address pointer
Cleared on reset. Pointer updated by DMA during operation.
313029282726252423222120191817161514131211109876543210
HRBAP
rrrrrrrrrrrrrrrrrrrrrrrrrrrrrrrr
Bits 31:0 HRBAP: Host receive buffer address pointer
Cleared on reset. Pointer updated by DMA during operation.
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