AMD Elan SC520 - Page 433

Index
Élan™SC520 Microcontroller User’s Manual Index-19
registers (continued)
Master Software DRQ(n) Request
(MSTDMASWREQ), 14-7
PCI Bus Arbiter Status (PCIARBSTA), 8-2
PCI Configuration Address (PCICFGADR), 9-8
PCI Configuration Data (PCICFGDATA), 9-8
PCI Host Bridge Interrupt Mapping
(PCIHOSTMAP), 15-4
PCI Interrupt A Mapping (PCIINTAMAP), 15-5
PCI Interrupt B Mapping (PCIINTBMAP), 15-5
PCI Interrupt C Mapping (PCIINTCMAP), 15-5
PCI Interrupt D Mapping (PCIINTDMAP), 15-5
PIO15–PIO0 Clear (PIOCLR15_0), 23-4
PIO15–PIO0 Data (PIODATA15_0), 23-4
PIO15–PIO0 Direction (PIODIR15_0), 23-4
PIO15–PIO0 Pin Function Select
(PIOPFS15_0), 23-4
PIO15–PIO0 Set (PIOSET15_0), 23-4
PIO31–PIO16 Clear (PIOCLR31_16), 23-4
PIO31–PIO16 Data (PIODATA31_16), 23-4
PIO31–PIO16 Direction (PIODIR31_16), 23-4
PIO31–PIO16 Pin Function Select
(PIOPFS31_16), 23-4
PIO31–PIO16 Set (PIOSET31_16), 23-4
PIT Channel x Count (PITxCNT), 16-3
PIT Counter Latch Command (PITCNTLAT), 16-3
PIT Mode Control (PITMODECTL), 16-3
PIT Read-Back Command (PITRDBACK), 16-3
PIT x Interrupt Mapping (PITxMAP), 15-4
PIT x Status (PITxSTA), 16-3
Programmable Address Region x (PARx), 4-2
Reset Configuration (RESCFG), 6-3
Reset Status (RESSTA), 6-3
ROMCS1
Control (ROMCS1CTL), 12-5
ROMCS2
Control (ROMCS2CTL), 12-5
RTC Alarm Hour (RTCALMHR), 20-6
RTC Alarm Minute (RTCALMMIN), 20-6
RTC Alarm Second (RTCALMSEC), 20-6
RTC Control A (RTCCTLA), 20-7
RTC Control B (RTCCTLB), 20-7
RTC Current Day of the Month
(RTCCURDOM), 20-6
RTC Current Day of the Week
(RTCCURDOW), 20-6
RTC Current Hour (RTCCURHR), 20-6
RTC Current Minute (RTCCURMIN), 20-6
RTC Current Month (RTCCURMON), 20-6
RTC Current Second (RTCCURSEC), 20-6
RTC Current Year (RTCCURYR), 20-6
RTC Interrupt Mapping (RTCMAP), 15-5
RTC Status C (RTCSTAC), 20-7
RTC Status D (RTCSTAD), 20-7
RTC/CMOS RAM Data Port (RTCDATA), 20-6
RTC/CMOS RAM Index (RTCIDX), 20-6
SCP Command Port (SCPCMD), 6-3
SCP Data Port (SCPDATA), 6-3
registers (continued)
SDRAM Bank 0–3 Ending Address
(DRCBENDADR), 10-10
SDRAM Bank Configuration (DRCCFG), 10-10
SDRAM Buffer Control (DBCTL), 11-4
SDRAM Control (DRCCTL), 10-10
SDRAM Timing Control (DRCTMCTL), 10-10
Slave DMA Channel 0–3 Control
(SLDMACTL), 14-7
Slave DMA Channel 0–3 Mask (SLDMAMSK), 14-7
Slave DMA Channel 0–3 Mode
(SLDMAMODE), 14-7
Slave DMA Channel 0–3 Status (SLDMASTA), 14-7
Slave DMA Channel x Memory Address
(GPDMAxMAR), 14-7
Slave DMA Channel x Page (GPDMAxPG), 14-7
Slave DMA Channel x Transfer Count
(GPDMAxTC), 14-7
Slave DMA Clear Byte Pointer (SLDMACBP), 14-7
Slave DMA Controller Reset (SLDMARST), 14-8
Slave DMA Controller Temporary
(SLDMATMP), 14-8
Slave DMA General Mask (SLDMAGENMSK), 14-8
Slave DMA Mask Reset (SLDMAMSKRST), 14-8
Slave Software DRQ(n) Request
(SLDMASWREQ), 14-7
Slave x PIC Initialization Control Word 1
(SxPICICW1), 15-6
Slave x PIC Initialization Control Word 2
(SxPICICW2), 15-6
Slave x PIC Initialization Control Word 3
(SxPICICW3), 15-7
Slave x PIC Initialization Control Word 4
(SxPICICW4), 15-7
Slave x PIC In-Service (SxPICISR), 15-6
Slave x PIC Interrupt Mask (SxPICINTMSK), 15-7
Slave x PIC Interrupt Mode (SLxPICMODE), 15-4
Slave x PIC Interrupt Request (SxPICIR), 15-6
Slave x PIC Operation Control Word 2
(SxPICOCW2), 15-6
Slave x PIC Operation Control Word 3
(SxPICOCW3), 15-6
Software Interrupt 16–1 Control (SWINT16_1), 15-4
Software Interrupt 22–17/NMI Control
(SWINT22_17), 15-4
Software Timer Configuration (SWTMRCFG), 18-2
Software Timer Microsecond Count
(SWTMRMICRO), 18-2
Software Timer Millisecond Count
(SWTMRMILLI), 18-2
SSI Command (SSICMD), 22-2
SSI Control (SSICTL), 22-2
SSI Interrupt Mapping (SSIMAP), 15-5
SSI Receive (SSIRCV), 22-2
SSI Status (SSISTA), 22-2
SSI Transmit (SSIXMIT), 22-2
Status/Command (PCISTACMD), 9-8