Index
Index-20 Élan™SC520 Microcontroller User’s Manual
registers (continued)
System Arbiter Control (SYSARBCTL), 8-2
System Arbiter Master Enable
(SYSARBMENB), 8-2
System Board Information (SYSINFO), 6-3
System Control Port A (SYSCTLA), 6-3
System Control Port B (SYSCTLB), 16-3
UART x Baud Clock Divisor Latch LSB
(UARTxBCDL), 21-4
UART x Baud Clock Divisor Latch MSB
(UARTxBCDH), 21-4
UART x FIFO Control (UARTxFCR), 21-4
UART x FIFO Control Shadow
(UARTxFCRSHAD), 21-3
UART x General Control (UARTxCTL), 21-3
UART x General Status (UARTxSTA), 21-3
UART x Interrupt Enable (UARTxINTENB), 21-4
UART x Interrupt ID (UARTxINTID), 21-4
UART x Interrupt Mapping (UARTxMAP), 15-5
UART x Line Control (UARTxLCR), 21-4
UART x Line Status (UARTxLSR), 21-4
UART x Modem Control (UARTxMCR), 21-4
UART x Modem Status (UARTxMSR), 21-4
UART x Receive Buffer (UARTxRBR), 21-4
UART x Scratch Pad (UARTxSCRATCH), 21-4
UART x Transmit Holding (UARTxTHR), 21-4
Watchdog Timer Control (WDTMRCTL), 19-2
Watchdog Timer Count High
(WDTMRCNTH), 19-3, 19-6
Watchdog Timer Count Low (WDTMRCNTL), 19-2
Watchdog Timer Interrupt Mapping
(WDTMAP), 15-5
Write-Protect Violation Interrupt Mapping
(WPVMAP), 15-5
Write-Protect Violation Status (WPVSTA), 4-2
REQ4
–REQ0 signals
control, 2-7, 8-2
usage, 8-7
Request To Send signals.
See
RTS2–RTS1 signals.
RESCFG register, 6-3
Reset Configuration (RESCFG) register
function, 6-3, 10-10, 13-6, 24-2
usage, 6-4, 6-5, 6-6, 6-7, 10-29, 13-22, 24-11
reset generation
a20 gate support, 6-8
block diagram (figure), 6-2
core states after system reset (table), 6-5
determining reset sources, 6-8
GP bus reset, 6-7
hard CPU reset, 7-5
initialization, 6-9
latency, 6-9
operation, 6-3
overview, 6-1
PCI reset, 6-7
PLL start-up, 6-8
PLL start-up timing (figure), 6-9
power-on reset, 6-9
power-on reset timing (figure), 6-9
PRGRESET timing (figure), 6-6
programmable reset, 6-6, 10-29
registers, 6-3
reset sources (table), 6-4
reset types, 6-3
reset vector and reset segment, 3-4
RTC reset, 6-7
signal descriptions, 2-10
soft CPU reset, 6-7, 7-5
software considerations, 6-8
system design, 6-2
system reset, 6-4
system reset with SDRAM retention, 6-6
Reset Latched Input signals.
See
RSTLD7–RSTLD0
signals.
Reset signal.
See
RST signal.
Reset Status (RESSTA) register
function, 6-3, 7-1, 10-10, 19-3, 24-3
usage, 6-8, 24-11
RESSTA register, 6-3
REVID register, 7-1
RF_CLR bit field, 21-10
RFRT bit field, 21-7, 21-10
RFSH_ENB bit field, 10-19
RFSH_SPD bit field, 10-18
RIN2
–RIN1 signals
control, 13-6, 21-2, 21-3, 21-4
description, 2-9, 21-6
usage, 21-2, 21-9
Ring Indicate signals.
See
RIN2–RIN1 signals.
ROM Buffer Output Enable signal.
See
ROMBUFOE
signal.
ROM/Flash Boot Chip Select signal.
See
BOOTCS
signal.
ROM/Flash Chip Select signals.
See
ROMCS2–
ROMCS1
signals.
ROM/Flash controller
access timing and wait states example (table), 12-9
accesses and ROM width (table), 12-9
address decoding, 12-12
block diagram (figure), 12-2
bus cycles, 12-9
2 doublewords from 16-bit ROM (figure), 12-11
4 aligned doublewords from 32-bit ROM
(figure), 12-8
4 unaligned doublewords from 8-bit ROM
(figure), 12-8
4 words from 16-bit ROM (figures), 12-8
burst page access from 32-bit ROM
(figure), 12-10
cache-line fill (figure), 12-11
multiple accesses from 8-bit ROM (figure), 12-10
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