AMD Elan SC520 - Page 432

Index
Index-18 Élan™SC520 Microcontroller User’s Manual
registers (continued)
DMA Buffer Chaining Interrupt Mapping
(DMABCINTMAP), 14-4, 15-5
Drive Strength Control (DSCTL), 23-4
ECC Check Bit Position (ECCCKBPOS), 10-10
ECC Check Code Test (ECCCKTEST), 10-10
ECC Control (ECCCTL), 10-10
ECC Interrupt Mapping (ECCMAP), 15-4
ECC Multi-Bit Error Address (ECCMBADD), 10-10
ECC Single-Bit Error Address (ECCSBADD), 10-10
ECC Status (ECCSTA), 10-10
ÉlanSC520 Microcontroller Revision ID
(REVID), 7-1
Floating Point Error Interrupt Clear
(FPUERRCLR), 15-7
Floating Point Error Interrupt Mapping
(FERRMAP), 15-5
General-Purpose CMOS RAM (RTCCMOS), 20-7
GP ALE Offset (GPALEOFF), 13-6
GP ALE Pulse Width (GPALEW), 13-6
GP Chip Select Data Width (GPCSDW), 13-5
GP Chip Select Offset (GPCSOFF), 13-5
GP Chip Select Pulse Width (GPCSPW), 13-5
GP Chip Select Qualification (GPCSQUAL), 13-5
GP Chip Select Recovery Time (GPCSRT), 13-5
GP Echo Mode (GPECHO), 13-5
GP Read Offset (GPRDOFF), 13-5
GP Read Pulse Width (GPRDW), 13-5
GP Timer x Count (GPTMRxCNT), 17-2, 17-3
GP Timer x Interrupt Mapping (GPTMRxMAP), 15-4
GP Timer x Maxcount Compare A
(GPTMRxMAXCMPA), 17-2, 17-3
GP Timer x Maxcount Compare B
(GPTMRxMAXCMPB), 17-2, 17-3
GP Timer x Mode/Control
(GPTMRxCTL), 17-2, 17-3
GP Timers Status (GPTMRSTA), 17-2
GP Write Offset (GPWROFF), 13-6
GP Write Pulse Width (GPWRW), 13-5
GP-DMA Channel x Extended Page
(GPDMAEXTPGx), 14-4, 14-5
GP-DMA Channel x Extended Transfer Count
(GPDMAEXTTCx), 14-5
GP-DMA Channel x Next Address High
(GPDMANXTADDHx), 14-5, 14-6
GP-DMA Channel x Next Address Low
(GPDMANXTADDLx), 14-5, 14-6
GP-DMA Channel x Next Transfer Count High
(GPDMANXTTCHx), 14-6
GP-DMA Channel x Next Transfer Count Low
(GPDMANXTTCLx), 14-6
GP-DMA Control (GPDMACTL), 14-4
GP-DMA Memory-Mapped I/O
(GPDMAMMIO), 14-4
GP-DMA Resource Channel Map A
(GPDMAEXTCHMAPA), 14-4
registers (continued)
GP-DMA Resource Channel Map B
(GPDMAEXTCHMAPB), 14-4
GPIRQx Interrupt Mapping (GPxIMAP), 15-5
Header Type (PCIHEADTYPE), 9-8
Host Bridge Control (HBCTL), 9-7
Host Bridge Master Interrupt Address
(MSTINTADD), 9-7
Host Bridge Master Interrupt Control
(HBMSTIRQCTL), 9-7
Host Bridge Master Interrupt Status
(HBMSTIRQSTA), 9-7
Host Bridge Target Interrupt Control
(HBTGTIRQCTL), 9-7
Host Bridge Target Interrupt Status
(HBTGTIRQSTA), 9-7
Interrupt Control (PICICR), 15-4
Interrupt Pin Polarity (INTPINPOL), 15-4
Master DMA Channel 4–7 Control
(MSTDMACTL), 14-7
Master DMA Channel 4–7 Mask
(MSTDMAMSK), 14-7
Master DMA Channel 4–7 Mode
(MSTDMAMODE), 14-7
Master DMA Channel 4–7 Status
(MSTDMASTA), 14-7
Master DMA Channel x Memory Address
(GPDMAxMAR), 14-7
Master DMA Channel x Page (GPDMAxPG), 14-7
Master DMA Channel x Transfer Count
(GPDMAxTC), 14-7
Master DMA Clear Byte Pointer
(MSTDMACBP), 14-7
Master DMA Controller Reset (MSTDMARST), 14-8
Master DMA Controller Temporary
(MSTDMATMP), 14-8
Master DMA General Mask
(MSTDMAGENMSK), 14-8
Master DMA Mask Reset (MSTDMAMSKRST), 14-8
Master PIC Initialization Control Word 1
(MPICICW1), 15-6
Master PIC Initialization Control Word 2
(MPICICW2), 15-6
Master PIC Initialization Control Word 3
(MPICICW3), 15-7
Master PIC Initialization Control Word 4
(MPICICW4), 15-7
Master PIC In-Service (MPICISR), 15-6
Master PIC Interrupt Mask (MPICINTMSK), 15-7
Master PIC Interrupt Mode (MPICMODE), 15-4
Master PIC Interrupt Request (MPICIR), 15-6
Master PIC Operation Control Word 2
(MPICOCW2), 15-6
Master PIC Operation Control Word 3
(MPICOCW3), 15-6
Master Retry Time-Out (PCIMRETRYTO), 9-8