Index
Élan™SC520 Microcontroller User’s Manual Index-17
clocking considerations, 16-6
external clock source (table), 16-6
internal clock source (table), 16-6
initialization, 16-7
interrupts, 16-6
operating modes, 16-4
hardware-retriggerable one-shot, 16-4
hardware-triggered strobe, 16-5
interrupt on terminal count, 16-4
rate generator, 16-5
software-triggered strobe, 16-5
square wave mode, 16-5
operation, 16-3
overview, 16-1
PIT Channel 0, 16-3
PIT Channel 1, 16-3
PIT Channel 2, 16-4
registers, 16-2
signal descriptions, 2-10
software considerations, 16-6
PC/AT-compatible systems, 16-6
system design, 16-1
shared signals (table), 16-1
Programmable Interval Timer 2 Gate signal.
See
PITGATE2 signal.
Programmable Interval Timer 2 Output signal.
See
PITOUT2 signal.
programmable reset, 6-6, 10-29
Programmable Reset signal.
See
PRGRESET signal.
PSC_SEL bit field, 17-3
pulldown resistors
configuration signals, 2-13
ECC devices not installed, 10-9
internal value, 2-4
JTAG boundary scan test interface, 25-15
JTAG signals, 2-12
PIO31–PIO0 signals, 23-1–23-2
PIO31–PIO0 signals (table), 23-3
SSI devices, 22-1
pullup resistors
GP bus external pullups required, 13-4
GPRDY signal, 2-9
internal value, 2-4
JTAG boundary scan test interface, 25-4
JTAG signals, 2-12
PCI external pullups required, 9-3
PIO31–PIO0 signals, 23-1–23-2
PIO31–PIO0 signals (table), 23-3
SSI devices, 22-1
UART serial port signals, 21-2
PWRGOOD signal
description, 2-10
timing, 6-9
usage,6-2,6-4,6-8,20-5
PWRGOOD_DET bit field, 6-8
R
RAS_CAS_DLY bit field, 10-21
RAS_PCHG_DLY bit field, 10-21
RATE_SEL bit field, 20-8
read buffer.
See
write buffer and read buffer.
real-time clock (RTC)
block diagram (figure), 20-2
configuration, 20-7
alarm function, 20-9
date and time, 20-8
hour format, 20-7
periodic interrupts, 20-8
using RATE_SEL (table), 20-8
year 2000 issues, 20-9
disabling, 3-21
initialization, 20-10
RTC reset, 20-11
interrupts, 20-9
operation, 20-7
overview, 20-1
registers, 20-6
RTC reset, 6-7
software considerations, 20-10
accessing the CMOS memory, 20-10
initializing the RTC divider chain, 20-10
legacy NMI enable bit moved, 20-10
system design, 20-3
backup battery considerations, 20-3
circuit with backup battery (figure), 20-4
circuit without backup battery (figure), 20-5
external RTC, 20-5
selecting and interfacing a 32.768-kHz
crystal, 20-5
voltage monitor, 20-2
voltage monitor block diagram (figure), 20-3
register set manual, xxiv
REGISTER_NUM bit field, 9-10
registers
Address Decode Control (ADDDECCTL), 4-2
Am5
x
86 CPU Control (CPUCTL), 7-1
AMDebug Technology RX/TX Interrupt Mapping
(ICEMAP), 15-5
Arbiter Priority Control (ARBPRICTL), 8-2
BOOTCS
Control (BOOTCSCTL), 12-5
Buffer Chaining Control (GPDMABCCTL), 14-5
Buffer Chaining Interrupt Enable
(GPDMABSINTENB), 14-5
Buffer Chaining Status (GPDMABCSTA), 14-5
Buffer Chaining Valid (GPDMABCVAL), 14-5
Chip Select Pin Function Select (CSPFS), 23-4
Class Code/Revision ID (PCICCREVID), 9-8
Clock Select (CLKSEL), 5-6, 23-4
Configuration Base Address (CBAR), 4-2
Device/Vendor ID (PCIDEVID), 9-8
To Next Page
Loading...