Index
Index-16 Élan™SC520 Microcontroller User’s Manual
PIT x Interrupt Mapping (PITxMAP) register
function, 15-4, 16-2
PIT x Status (PITxSTA) register
function, 16-3
PIT.
See
programmable interval timer (PIT).
PIT_GATE2 bit field, 16-4
PIT_OUT2_ENB bit field, 16-4
PIT_OUT2_STA bit field, 16-4
PITCNTLAT register, 16-3
PITGATE2 signal
control, 13-3, 13-6, 16-1, 16-2, 16-4
description, 2-10
PITMODECTL register, 16-3
PITOUT2 signal
control, 16-3
description, 2-10
usage, 16-1, 16-4
PITRDBACK register, 16-3
PITxCNT register, 16-3
PITxMAP register, 15-4
PITxSTA register, 16-3
PLL.
See
clock generation and control.
See also
reset
generation.
power
signal descriptions, 2-14
Power Good signal.
See
PWRGOOD signal.
Power Supply signals.
See
VCC_CORE signal,
VCC_I/O signal, and VCC_RTC signal.
power-on reset, 6-9
PRG_RST_ENB bit field, 3-4, 6-4, 6-6, 10-29
PRGRESET signal
control, 6-3, 10-10
description, 2-10
timing (figure), 6-6
usage, 3-4, 6-4, 6-6, 6-8, 6-9, 10-10, 10-29
PRGRST_DET bit field, 6-8
Programmable Address Region x (PARx) registers
address region attributes, 3-12
cacheability control, 3-12
code execution control, 3-12
doubleword boundaries, 4-19
external GP bus devices, 3-13
external ROM devices, 3-17
format (figure), 3-10
function, 4-2, 24-2
maximum region size, 4-19
PAR register priority, 3-13
PCI bus devices, 3-15
performance considerations of attributes, 3-12
region size, 4-18
SDRAM regions, 3-18
software considerations, 4-17
specifying pages and regions, 3-9
start address, 4-18
usage, 2-11, 3-8, 3-10, 4-5, 12-14, 13-6, 13-9,
13-22, 15-9
worksheet (figure), 3-11
write-protection, 3-12
programmable input/output (PIO)
block diagram (figure), 23-2
configuration
configuration summary (table), 23-5
input pins, 23-5
output pins, 23-5
initialization, 23-6
operation, 23-4
overview, 23-1
PIO31–PIO0 signals, 23-4
registers, 23-4
signal descriptions, 2-11
software considerations, 23-5
system design, 23-2
shared signals (table), 23-3
Programmable Input/Output signals.
See
PIO31–PIO0
signals.
programmable interrupt controller (PIC)
block diagram (figure), 15-3
configuration, 15-16
PC/AT configuration, 15-18
programming, 15-16
configuring interrupt mapping, 3-19
edge-triggered or level-sensitive interrupts, 15-13
initialization, 15-20
interrupt flow sequence, 15-7
interrupt sharing, 15-13
interrupt source routing, 15-10
disabling the slave controllers, 15-13
floating point error handling, 15-12
PC/AT compatibility, 15-12
polarity inversion of interrupt requests, 15-10
interrupt source routing (figure), 15-11
interrupt sources, 15-8
hardware-generated interrupts, 15-8
interrupt sources (figure), 15-9
non-maskable interrupts and routing, 15-14
NMI routing (figure), 15-15
NMI sharing, 15-14
operation, 15-7
overview, 15-1
PC/AT interrupt channel mapping (table), 15-12
priority types, 15-16
registers, 15-4
software considerations, 15-18
detecting invalid interrupt requests, 15-19
disabling the slave controllers, 15-19
floating point unit error handling, 15-19
interrupt sharing, 15-18
system design, 15-2
shared signals (table), 15-2
programmable interval timer (PIT)
block diagram (figure), 16-2
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