ST STM32F101xx User Manual

RM0008 Ethernet (ETH): media access control (MAC) with DMA controller
Doc ID 13902 Rev 12 1007/1096
The Hash table high register contains the higher 32 bits of the multicast Hash table.
Ethernet MAC hash table low register (ETH_MACHTLR)
Address offset: 0x000C
Reset value: 0x0000 0000
The Hash table low register contains the lower 32 bits of the multi-cast Hash table.
Ethernet MAC MII address register (ETH_MACMIIAR)
Address offset: 0x0010
Reset value: 0x0000 0000
The MII address register controls the management cycles to the external PHY through the
management interface.
313029282726252423222120191817161514131211109876543210
HTH
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 HTH: Hash table high
This field contains the upper 32 bits of Hash table.
313029282726252423222120191817161514131211109876543210
HTL
rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw rw
Bits 31:0 HTL: Hash table low
This field contains the lower 32 bits of the Hash table.
31302928272625242322212019181716151413121110987654321 0
Reserved
PA MR
Reserved
CR MW MB
rw rw rw rw rw rw rw rw rw rw rw rw rw rw
rc_
w1
Bits 31:16 Reserved
Bits 15:11 PA : PHY address
This field tells which of the 32 possible PHY devices are being accessed.
Bits 10:6 MR: MII register
These bits select the desired MII register in the selected PHY device.
Bit 5 Reserved

ST STM32F101xx Specifications

General

Brand	ST
Model	STM32F101xx
Category	Microcontrollers
Language	English