General-purpose timers (TIM2 to TIM5) RM0008
404/1096 Doc ID 13902 Rev 12
Bits 15:0 DMAB[15:0]: DMA register for burst accesses
A read or write access to the DMAR register accesses the register located at the address:
“(TIMx_CR1 address) + DBA + (DMA index)” in which:
TIMx_CR1 address is the address of the control register 1,
DBA is the DMA base address configured in the TIMx_DCR register,
DMA index is the offset automatically controlled by the DMA transfer, depending on the
length of the transfer DBL in the TIMx_DCR register.
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