RM0008 Serial peripheral interface (SPI)
Doc ID 13902 Rev 12 691/1096
SPI communication using CRC is possible through the following procedure:
● Program the CPOL, CPHA, LSBFirst, BR, SSM, SSI and MSTR values
● Program the polynomial in the SPI_CRCPR register
● Enable the CRC calculation by setting the CRCEN bit in the SPI_CR1 register. This
also clears the SPI_RXCRCR and SPI_TXCRCR registers
● Enable the SPI by setting the SPE bit in the SPI_CR1 register
● Start the communication and sustain the communication until all but one byte or half-
word have been transmitted or received.
● In full duplex or transmitter-only mode, when the transfers are managed by software, on
writing the last byte or half word to the TX buffer, set the CRCNEXT bit in the SPI_CR1
register to indicate that after the transmission of the last byte, the CRC, is to be
transmitted. In receiver only mode, set the CRCNEXT bit just after the reception of the
second last data in order to prepare the SPI to enter the CRC phase at the end of the
reception of the last data. CRC calculation is frozen during the CRC transfer.
● After the transfer of the last byte or half word, the SPI enters the CRC transfer and
check phase. In full duplex mode or receiver-only mode, the received CRC is compared
to the SPI_RXCRCR value. If the value does not match, the CRCERR flag in SPI_SR is
set and an interrupt can be generated when the ERRIE bit in the SPI_CR2 register is
set.
Note: When the SPI is in slave mode, be careful to enable CRC calculation only when the clock is
stable, that is, when the clock is in the steady state. If not, a wrong CRC calculation may be
done. In fact, the CRC is sensitive to the SCK slave input clock as soon as CRCEN is set,
and this, whatever the value of the SPE bit.
With high bitrate frequencies, be careful when transmitting the CRC. As the number of used
CPU cycles has to be as low as possible in the CRC transfer phase, it is forbidden to call
software functions in the CRC transmission sequence to avoid errors in the last data and
CRC reception. In fact, CRCNEXT bit has to be written before the end of the
transmission/reception of the last data.
For high bit rate frequencies, it is advised to use the DMA mode to avoid the degradation of
the SPI speed performance due to CPU accesses impacting the SPI bandwidth.
When the STM32F10xxx areis configured as slaves and the NSS hardware mode is used,
the NSS pin needs to be kept low between the data phase and the CRC phase.
When the SPI is configured in slave mode with the CRC feature enabled, CRC calculation
takes place even if a high level is applied on the NSS pin. This may happen for example in
case of a multislave environment where the communication master addresses slaves
alternately.
Between a slave deselection (high level on NSS) and a new slave selection (low level on
NSS), the CRC value should be cleared on both master and slave sides in order to
resynchronize the master and slave for their respective CRC calculation.
To clear the CRC, follow the procedure below:
1. Disable SPI (SPE = 0)
2. Clear the CRCEN bit
3. Set the CRCEN bit
4. Enable the SPI (SPE = 1)
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