Inter-integrated circuit (I
2
C) interface RM0008
744/1096 Doc ID 13902 Rev 12
1. Set the I2C_DR register address in the DMA_CPARx register. The data will be moved
to this address from the memory after each TxE event.
2. Set the memory address in the DMA_CMARx register. The data will be loaded into
I2C_DR from this memory after each TxE event.
3. Configure the total number of bytes to be transferred in the DMA_CNDTRx register.
After each TxE event, this value will be decremented.
4. Configure the channel priority using the PL[0:1] bits in the DMA_CCRx register
5. Set the DIR bit and, in the DMA_CCRx register, configure interrupts after half transfer
or full transfer depending on application requirements.
6. Activate the channel by setting the EN bit in the DMA_CCRx register.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
I
2
C interface and the DMA generates an interrupt, if enabled, on the DMA channel interrupt
vector.
Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for transmission.
Reception using DMA
DMA mode can be enabled for reception by setting the DMAEN bit in the I2C_CR2 register.
Data will be loaded from the I2C_DR register to a Memory area configured using the DMA
peripheral (refer to the DMA specification) whenever a data byte is received. To map a DMA
channel for I
2
C reception, perform the following sequence. Here x is the channel number.
1. Set the I2C_DR register address in DMA_CPARx
register. The data will be moved from
this address to the memory after each RxNE event.
2. Set the memory address in the DMA_CMARx register. The data will be loaded from the
I2C_DR register to this memory area after each RxNE event.
3. Configure the total number of bytes to be transferred in the DMA_CNDTRx register.
After each RxNE event, this value will be decremented.
4. Configure the channel priority using the PL[0:1] bits in the DMA_CCRx register
5. Reset the DIR bit and configure interrupts in the DMA_CCRx register after half transfer
or full transfer depending on application requirements.
6. Activate the channel by setting the EN bit in the DMA_CCRx register.
When the number of data transfers which has been programmed in the DMA Controller
registers is reached, the DMA controller sends an End of Transfer EOT/ EOT_1 signal to the
I
2
C interface and DMA generates an interrupt, if enabled, on the DMA channel interrupt
vector.
Note: Do not enable the ITBUFEN bit in the I2C_CR2 register if DMA is used for reception.
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