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ST STM32F101xx User Manual

ST STM32F101xx
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Ethernet (ETH): media access control (MAC) with DMA controller RM0008
962/1096 Doc ID 13902 Rev 12
If the received frame length/type field is less than 0x600 and if the MAC is programmed for
the auto CRC/pad stripping option, the MAC sends the data of the frame to RxFIFO up to
the count specified in the length/type field, then starts dropping bytes (including the FCS
field). If the Length/Type field is greater than or equal to 0x600, the MAC sends all received
Ethernet frame data to Rx FIFO, regardless of the value on the programmed auto-CRC strip
option. The MAC watchdog timer is enabled by default, that is, frames above 2048 bytes (DA
+ SA + LT + Data + pad + FCS) are cut off. This feature can be disabled by programming the
watchdog disable (WD) bit in the MAC configuration register. However, even if the watchdog
timer is disabled, frames greater than 16 KB in size are cut off and a watchdog timeout
status is given.
Receive CRC: automatic CRC and pad stripping
The MAC checks for any CRC error in the receiving frame. It calculates the 32-bit CRC for
the received frame that includes the Destination address field through the FCS field. The
encoding is defined by the following polynomial.
Regardless of the auto-pad/CRC strip, the MAC receives the entire frame to compute the
CRC check for the received frame.
Receive checksum offload
Both IPv4 and IPv6 frames in the received Ethernet frames are detected and processed for
data integrity. You can enable the receive checksum offload by setting the IPCO bit in the
ETH_MACCR register. The MAC receiver identifies IPv4 or IPv6 frames by checking for
value 0x0800 or 0x86DD, respectively, in the received Ethernet frame Type field. This
identification applies to VLAN-tagged frames as well. The receive checksum offload
calculates IPv4 header checksums and checks that they match the received IPv4 header
checksums. The IP Header Error bit is set for any mismatch between the indicated payload
type (Ethernet Type field) and the IP header version, or when the received frame does not
have enough bytes, as indicated by the IPv4 header’s Length field (or when fewer than 20
bytes are available in an IPv4 or IPv6 header). The receive checksum offload also identifies
a TCP, UDP or ICMP payload in the received IP datagrams (IPv4 or IPv6) and calculates the
checksum of such payloads properly, as defined in the TCP, UDP or ICMP specifications. It
includes the TCP/UDP/ICMPv6 pseudo-header bytes for checksum calculation and checks
whether the received checksum field matches the calculated value. The result of this
operation is given as a Payload Checksum Error bit in the receive status word. This status
bit is also set if the length of the TCP, UDP or ICMP payload does not match the expected
payload length given in the IP header. As mentioned in TCP/UDP/ICMP checksum on
page 958, the receive checksum offload bypasses the payload of fragmented IP datagrams,
IP datagrams with security features, IPv6 routing headers, and payloads other than TCP,
UDP or ICMP. This information (whether the checksum is bypassed or not) is given in the
receive status, as described in the RDES0: Receive descriptor Word0 section. In this
configuration, the core does not append any payload checksum bytes to the received
Ethernet frames.
As mentioned in RDES0: Receive descriptor Word0 on page 995, the meaning of certain
register bits changes as shown in Table 2 1 0 .
Gx() x
32
x
26
x
23
x
22
x
16
x
12
x
11
x
10
x
8
x
7
x
5
x
4
x
2
x1+ + + + + + + +++++++=

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ST STM32F101xx Specifications

General IconGeneral
BrandST
ModelSTM32F101xx
CategoryMicrocontrollers
LanguageEnglish

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