ST STM32F405 User Manual

RM0090 Rev 18 1003/1749
RM0090 Universal synchronous asynchronous receiver transmitter (USART)
1018
Figure 316. Reception using DMA
Error flagging and interrupt generation in multibuffer communication
In case of multibuffer communication if any error occurs during the transaction the error flag
will be asserted after the current byte. An interrupt will be generated if the interrupt enable
flag is set. For framing error, overrun error and noise flag which are asserted with RXNE in
case of single byte reception, there will be separate error flag interrupt enable bit (EIE bit in
the USART_CR3 register), which if set will issue an interrupt after the current byte with
either of these errors.
30.3.14 Hardware flow control
It is possible to control the serial data flow between 2 devices by using the CTS input and
the RTS output. The Figure 317 shows how to connect 2 devices in this mode:
Figure 317. Hardware flow control between 2 USARTs
RTS and CTS flow control can be enabled independently by writing respectively RTSE and
CTSE bits to 1 (in the USART_CR3 register).
TX line
USART_DR
Frame 1
RXNE flag
F2 F3
Frame 2
Frame 3
set by hardware
cleared by DMA read
F1
software configures the
DMA to receive 3 data
blocks and enables
the USART
DMA request
DMA reads USART_DR
DMA TCIF flag
set by hardware
cleared
by software
DMA reads F1
from
USART_DR
(Transfer complete)
DMA reads F2
from
USART_DR
DMA reads F3
from
USART_DR
The DMA transfer
is complete
(TCIF=1 in
DMA_ISR)
ai17193b
MSv31169V2
TX circuit
USART 1
TX
RX circuit
RX circuit
USART 2
TX circuit
TX
CTS
CTSRTS
RX
RTS
RX

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English