ST STM32F405 User Manual

Revision history RM0090
1742/1749 RM0090 Rev 18
20-Sep-2016
13
(continued)
FMC
Update BUSTURN bit description in Section : SRAM/NOR-Flash chip-select timing
registers 1..4 (FMC_BTR1..4) and Section : SRAM/NOR-Flash write timing
registers 1..4 (FMC_BWTR1..4).
Debug support
Specified behavior of timers with complementary outputs in Section 38.16.2: Debug
support for timers, watchdog, bxCAN and I
2
C.
Updated DBG_TIMx_STOP bit description in Section 38.16.4: Debug MCU APB1
freeze register (DBGMCU_APB1_FZ) and Section 38.16.4: Debug MCU APB1
freeze register (DBGMCU_APB1_FZ).
Electronic signature
Updated Section 39.1: Unique device ID register (96 bits).
21-Apr-2017 14
Updated:
– Section 5.5.2: PWR power control/status register (PWR_CSR) for STM32F42xxx
and STM32F43xxx
– Section 6.3.14: RCC APB2 peripheral clock enable register (RCC_APB2ENR)
– Section 14.3.5: DAC output voltage
– Section 38.6.1: MCU device ID code
– Figure 237: RTC block diagram
Deleted:
– Section 7.3.15: RCC APB2 peripheral clock enable register(RCC_APB2ENR)
18-Jul-2017 15
Updated:
– Section 3.9.10: Flash option control register (FLASH_OPTCR) for STM32F42xxx
and STM32F43xxx
– OTG_FS USB configuration register (OTG_FS_GUSBCFG)
– Table 142: Error calculation for programmed baud rates at fPCLK = 42 MHz or
fPCLK = 84 Hz, oversampling by 16 and Table 143: Error calculation for
programmed baud rates at fPCLK = 42 MHz or fPCLK = 84 MHz, oversampling
by 8
23-Apr-2018 16
Updated:
– Section 30.6.1: Status register (USART_SR)
– Section 34.16.4: Device-mode registers
– Section 34.17.6: Operational model
– Section 35.12.4: Device-mode registers
– Section 34: USB on-the-go full-speed (OTG_FS)
– Table 199: Host-mode control and status registers (CSRs)
– Table 205: OTG_FS register map and reset values
– Table 210: Device-mode control and status registers
– Table 215: OTG_HS register map and reset values
Added:
– Figure 412: SOF trigger output to TIM2 ITR1 connection
RXOLNY register changed from SPI_CR2 to SPI_CR1 in Section 28.3.4:
Configuring the SPI for half-duplex communication and Unidirectional receive-only
procedure (BIDIMODE=0 and RXONLY=1)
Table 315. Document revision history (continued)
Date Version Changes

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English