RM0090 Rev 18 1719/1749
RM0090 Revision history
1743
19-Oct-2012
2
(continued)
RTC:
Updated Figure 237: RTC block diagram.
Added formula to compute
fck_apre in Figure 26.3.1: Clock and prescalers.
Updated Section 26.3.9: RTC reference clock detection.
Updated Section : RTC register write protection.
Added RTC_SSR shadow register in Section 26.3.6: Reading the calendar.
Updated description of DC[4:0] bits in Section 26.6.7: RTC calibration register
(RTC_CALIBR).
Renamed RTC_BKxR into RTC_BKPxR in Table 121: RTC register map and reset
values.
Added power-on reset value and changed reset value to system
reset value in Section 26.6.11: RTC sub second register (RTC_SSR).
Updated definition of ALARMOUTTYPE in Section 26.6.17: RTC tamper and
alternate function configuration register (RTC_TAFCR).
I2C:
Modified Section 27.3.8: DMA requests.
Updated bit 14 description in Section 27.6.3: I
2
C Own address register 1
(I2C_OAR1)).
Updated definition of PE bit and note related to SWRST bit; moved
note related to STOP bit to the whole register in Section 27.6.1: I
2
C Control register
1 (I2C_CR1).
USART:
Section 30.6.6: Control register 3 (USART_CR3)): removed notes
related to UART5 in DMAT and DMAR description.
Updated TTable 142: Error calculation for programmed baud rates at fPCLK = 42
MHz or fPCLK = 84 Hz, oversampling by 16 and
Table 143: Error calculation for programmed baud rates at fPCLK = 42 MHz or
fPCLK = 84 MHz, oversampling by 8.
SPI/I2S:
Updated Section 28.1: SPI introduction.
Changed I2S simplex communication/mode to half-duplex communication/mode.
Updated flags in reception/transmission modes in Section 28.2.2: I
2
S features.
Added Frame error flag in Table 128: I
2
S interrupt requests.
Added register access in Section 28.5: SPI and I
2
S registers.
Updated ERRIE definition in Section 28.5.2: SPI control register 2 (SPI_CR2).
Renamed TIFRFE to FRE and definition updated in Section 28.5.3: SPI status
register (SPI_SR).
Table 315. Document revision history (continued)
Date Version Changes