RM0090 Rev 18 595/1749
RM0090 General-purpose timers (TIM2 to TIM5)
649
Figure 141. Counter timing diagram, Update event when ARPE=0 (TIMx_ARR not
preloaded)
Figure 142. Counter timing diagram, Update event when ARPE=1 (TIMx_ARR
preloaded)
Downcounting mode
In downcounting mode, the counter counts from the auto-reload value (content of the
TIMx_ARR register) down to 0, then restarts from the auto-reload value and generates a
counter underflow event.
An Update event can be generate at each counter underflow or by setting the UG bit in the
TIMx_EGR register (by software or by using the slave mode controller)
The UEV update event can be disabled by software by setting the UDIS bit in TIMx_CR1
register. This is to avoid updating the shadow registers while writing new values in the
FF 36
MSv37303V1
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
00 02 03 04 05 06 0732 33 34 35 3631 01
CNT_EN
Auto-reload register
Write a new value in TIMx_ARR
MSv37304V1
F5 36
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
00 02 03 04 05 06 07F1 F2 F3 F4 F5F0 01
CNT_EN
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload shadow register
F5 36
To Next Page
Loading...
Need help?
General
