USB on-the-go high-speed (OTG_HS) RM0090
1398/1749 RM0090 Rev 18
The dynamic power consumption due to the USB clock switching activity is cut
even if the clock input is kept running by the application
– Most of the transceiver is also disabled, and only the part in charge of detecting
the asynchronous resume or remote wakeup event is kept alive.
• Gate HCLK (GATEHCLK bit in OTG_HS_PCGCCTL)
When setting the Gate HCLK bit in the clock gating control register, most of the system
clock domain internal to the OTG_HS core is switched off by clock gating. Only the
register read and write interface is kept alive. The dynamic power consumption due to
the USB clock switching activity is cut even if the system clock is kept running by the
application for other purposes.
• USB system stop
– When the OTG_HS is in USB suspended state, the application can decide to
drastically reduce the overall power consumption by shutting down all the clock
sources in the system. USB System Stop is activated by first setting the Stop PHY
clock bit and then configuring the system deep sleep mode in the powercontrol
system module (PWR).
– The OTG_HS core automatically reactivates both system and USB clocks by
asynchronous detection of remote wakeup (as an host) or resume (as a Device)
signaling on the USB.
35.9 Dynamic update of the OTG_HS_HFIR register
The USB core embeds a dynamic trimming capability of micro-SOF framing period in host
mode allowing to synchronize an external device with the micro-SOF frames.
When the OTG_HS_HFIR register is changed within a current micro-SOF frame, the SOF
period correction is applied in the next frame as described in Figure 413.
Figure 413. Updating OTG_HS_HFIR dynamically
400
…
…
… ……
450
Latency
SOF
reload
OTG_HS_HFIR
write
value
Frame
timer
Old OTG_HS_HIFR value
= 400 periods
OTG_HS_HIFR value
= 450 periods+HIFR write latency
New OTG_HS_HIFR value
= 450 periods
1
400
0
399
1
400
0
399
450
449
1
450
0
449
1
450
0
449
OTG_HS_HFIR
ai18439b
To Next Page
Loading...
Need help?
General
