ST STM32F405 User Manual

Embedded Flash memory interface RM0090
90/1749 RM0090 Rev 18
Option bytes (word, address 0x1FFF C008)
Bits 15:12 0xF: Not used
nWRP: Flash memory write protection option bytes
Sectors 0 to 11 can be write protected.
Bits 11:0
nWRPi
0: Write protection active on selected sector
1: Write protection not active on selected sector
Table 16. Description of the option bytes
(STM32F42xxx and STM32F43xxx)
Option bytes (word, address 0x1FFF C000)
RDP: Read protection option byte.
The read protection is used to protect the software code stored in Flash memory.
Bit 15:8
0xAA: Level 0, no protection
0xCC: Level 2, chip protection (debug and boot from RAM features
disabled)
Others: Level 1, read protection of memories (debug features limited)
USER: User option byte
This byte is used to configure the following features:
Select the watchdog event: Hardware or software
Reset event when entering the Stop mode
Reset event when entering the Standby mode
Bit 7
nRST_STDBY
0: Reset generated when entering the Standby mode
1: No reset generated
Bit 6
nRST_STOP
0: Reset generated when entering the Stop mode
1: No reset generated
Bit 5
WDG_SW
0: Hardware independent watchdog
1: Software independent watchdog
Bit 4
BFB2: Dual bank boot
0: Boot from Flash memory bank 1 or system memory depending on boot pin
state (Default).
1: Boot always from system memory (Dual bank boot mode).
Table 15. Description of the option bytes (STM32F405xx/07xx and
STM32F415xx/17xx) (continued)

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English