Flexible memory controller (FMC) RM0090
1624/1749 RM0090 Rev 18
Figure 464. ModeB write access waveforms
The differences with mode1 are the toggling of NWE and the independent read and write
timings when extended mode is set (Mode B).
Table 274. FMC_BCRx bit fields
Bit
number
Bit name Value to set
31-21 Reserved 0x000
20 CCLKEN As needed
19 CBURSTRW 0x0 (no effect in asynchronous mode)
18:16 CPSIZE 0x0 (no effect in asynchronous mode)
15 ASYNCWAIT
Set to 1 if the memory supports this feature. Otherwise keep at
0.
14 EXTMOD 0x1 for mode B, 0x0 for mode 2
13 WAITEN 0x0 (no effect in asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 WRAPMOD 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1
A[25:0]
NOE
ADDSET (DATAST + 1)
Memory transaction
NEx
D[31:0]
HCLK cycles HCLK cycles
NWE
NADV
data driven by FSMC
MS30458V1.
1HCLK
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