ST STM32F405 User Manual

Flexible memory controller (FMC) RM0090
1604/1749 RM0090 Rev 18
Figure 456. FMC block diagram
37.3 AHB interface
The AHB slave interface allows internal CPUs and other bus master peripherals to access
the external memories.
AHB transactions are translated into the external device protocol. In particular, if the
selected external memory is 16- or 8-bit wide, 32-bit wide transactions on the AHB are split
into consecutive 16- or 8-bit accesses. The FMC Chip Select (FMC_NEx) does not toggle
between consecutive accesses except when performing accesses in mode D with the
extended mode enabled.
MS30443V5
HCLK
NAND/PC Card
memory
controller
NAND
signals
Shared
signals
NOR/PSRAM
signals
FMC_NE[4:1]
FMC_NL(or NADV)
FMC_NWAIT
FMC_D[
31:0]
FMC_NOE
FMC_NWE
FMC_NIORD
FMC_NREG
FMC_CD
PC Card
signals
FMC_NBL[3:0]
FMC_NCE[3:2]
FMC_INT[3:2]
FMC_INTR
FMC_NCE4_1
FMC_NCE4_2
FMC_NIOWR
FMC_CLK
SDRAM
controller
FMC_SDNWE
FMC_SDCKE[1:0]
FMC_SDNE[1:0]
FMC_NRAS
FMC_NCAS
SDRAM
signals
FMC_A[25:0]
NOR/PSRAM/SRAM
Shared signals
SRAM/PSRAM/SDRAM
Shared signals
FMC_SDCLK
FMC interrupts to NVIC
From clock
controller
Configuration
registers
NOR/PSRAM
memory
controller

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English