ST STM32F405 User Manual

RM0090 Rev 18 305/1749
RM0090 DMA controller (DMA)
338
See Figure 33 and Figure 34 for the implementation of the system of two DMA controllers.
Figure 33. System implementation of the two DMA controllers
(STM32F405xx/07xx and STM32F415xx/17xx)
1. The DMA1 controller AHB peripheral port is not connected to the bus matrix like DMA2 controller. As a result, only DMA2
streams are able to perform memory-to-memory transfers.
MS19927V2
DMA controller 1
AHB periph
Arbiter
AHB memory
FIFO
DMA controller 2
AHB memory
Bus matrix
(AHB
Arbiter
AHB periph
MAPPING
FIFO
External memory
Flash
memory
112 KB SRAM
AHB2 peripherals
multilayer)
AHB-APB
bridge2
(dual AHB)
APB2
APB2
AHB-APB
bridge1
(dual AHB)
APB1
APB1
peripherals
AHB slaveAHB slave
portportportport
controller (FSMC)
DMA request
peripherals
16 KB SRAM
AHB1 peripherals
To AHB2 peripherals
To AHB2 peripherals
DCODE
ICODE

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English