ST STM32F405

Flexible static memory controller (FSMC) RM0090
1570/1749 RM0090 Rev 18
Figure 449. Asynchronous wait during a read access
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
Figure 450. Asynchronous wait during a write access
1. NWAIT polarity depends on WAITPOL bit setting in FSMC_BCRx register.
A[25:0]
NOE
4HCLK
Memory transaction
NWAIT
D[15:0]
NEx
data driven
by memory
ai18471b
address phase
don’t care
data setup phase
don’t care
A[25:0]
NWE
Memory transaction
NWAIT
D[15:0]
NEx
data driven by FSMC
ai15797c
3HCLK
address phase
data setup phase
1HCLK
don’t care don’t care