Power controller (PWR) RM0090
126/1749 RM0090 Rev 18
STM32F405xx/07xx and STM32F415xx/17xx and PWR power control register (PWR_CR)
for STM32F42xxx and STM32F43xxx.
The PVD is enabled by setting the PVDE bit.
A PVDO flag is available, in the PWR power control/status register (PWR_CSR) for
STM32F405xx/07xx and STM32F415xx/17xx, to indicate if V
DD
is higher or lower than the
PVD threshold. This event is internally connected to the EXTI line16 and can generate an
interrupt if enabled through the EXTI registers. The PVD output interrupt can be generated
when V
DD
drops below the PVD threshold and/or when V
DD
rises above the PVD threshold
depending on EXTI line16 rising/falling edge configuration. As an example the service
routine could perform emergency shutdown tasks.
Figure 14. PVD thresholds
5.3 Low-power modes
By default, the microcontroller is in Run mode after a system or a power-on reset. In Run
mode the CPU is clocked by HCLK and the program code is executed. Several low-power
modes are available to save power when the CPU does not need to be kept running, for
example when waiting for an external event. It is up to the user to select the mode that gives
the best compromise between low-power consumption, short startup time and available
wakeup sources.
The devices feature three low-power modes:
• Sleep mode (Cortex
®
-M4 with FPU core stopped, peripherals kept running)
• Stop mode (all clocks are stopped)
• Standby mode (1.2 V domain powered off)
MS30432V2
VDD
100 mV
hysteresis
PVD threshold
PVD output
To Next Page
Loading...
Need help?
General
