ST STM32F405 User Manual

Flexible memory controller (FMC) RM0090
1680/1749 RM0090 Rev 18
37.8 FMC register map
The following table summarizes the FMC registers.
Bits 2:1 MODES1[1:0]: Status Mode for Bank 1
This bit defines the Status Mode of SDRAM Bank 1.
00: Normal Mode
01: Self-refresh mode
10: Power-down mode
Bit 0 RE: Refresh error flag
0: No refresh error has been detected
1: A refresh error has been detected
An interrupt is generated if REIE = 1 and RE = 1
Table 297. FMC register map
Offset Register
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
11
10
9 8 7 6 5 4 3 2 1 0
0x00 FMC_BCR1 Reserved
CCLKEN
CBURSTRW
CPSIZE[2:0]
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID[1:0] MTYP[1:0]
MUXEN
MBKEN
0x08 FMC_BCR2 Reserved
CBURSTRW
CPSIZE[2:0]
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID[1:0] MTYP[1:0]
MUXEN
MBKEN
0x10 FMC_BCR3 Reserved
CBURSTRW
CPSIZE[2:0]
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID[1:0] MTYP[1:0]
MUXEN
MBKEN
0x18 FMC_BCR4 Reserved
CBURSTRW
CPSIZE[2:0]
ASYNCWAIT
EXTMOD
WAITEN
WREN
WAITCFG
WRAPMOD
WAITPOL
BURSTEN
Reserved
FACCEN
MWID[1:0] MTYP[1:0]
MUXEN
MBKEN
0x04 FMC_BTR1 Res.
ACCMOD[1:0
DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x0C FMC_BTR2
Res.
ACCMOD[1:0
DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x14 FMC_BTR3
Res.
ACCMOD[1:0
DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x1C FMC_BTR4
Res.
ACCMOD[1:0
DATLAT[3:0] CLKDIV[3:0] BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]
0x104 FMC_BWTR1
Res.
ACCMOD[1:0
Res. BUSTURN[3:0] DATAST[7:0] ADDHLD[3:0] ADDSET[3:0]

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English