ST STM32F405

RM0090 Rev 18 1611/1749
RM0090 Flexible memory controller (FMC)
1682
)
Table 261. SDRAM address mapping with 16-bit data bus width
(1)(2)
Row size
Configuration
HADDR(AHB address Lines)
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
11
10
9 8 7 6 5 4 3 2 1 0
11-bit row size
configuration
Res.
Bank
[1:0]
Row[10:0] Column[7:0] BM0
(3)
Res.
Bank
[1:0]
Row[10:0] Column[8:0] BM0
Res.
Bank
[1:0]
Row[10:0] Column[9:0] BM0
Res.
Bank
[1:0]
Row[10:0] Column[10:0] BM0
12-bit row size
configuration
Res.
Bank
[1:0]
Row[11:0] Column[7:0] BM0
Res.
Bank
[1:0]
Row[11:0] Column[8:0] BM0
Res.
Bank
[1:0]
Row[11:0] Column[9:0] BM0
Res.
Bank
[1:0]
Row[11:0] Column[10:0] BM0
13-bit row size
configuration
Res.
Bank
[1:0]
Row[12:0] Column[7:0] BM0
Res.
Bank
[1:0]
Row[12:0] Column[8:0] BM0
Res.
Bank
[1:0]
Row[12:0] Column[9:0] BM0
Re
s.
Bank
[1:0]
Row[12:0] Column[10:0] BM0
1. BANK[1:0] are the Bank Address BA[1:0]. When only 2 internal banks are used, BA1 must always be set to ‘0’.
2. Access to Reserved space (Res.) generates an AHB error.
3. BM0: is the byte mask for 16-bit access.
Table 262. SDRAM address mapping with 32-bit data bus width
(1)(2)
Row size
configuration
HADDR(AHB address Lines)
27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12
11
10
9 8 7 6 5 4 3 2 1 0
11-bit row size
configuration
Res.
Bank
[1:0]
Row[10:0] Column[7:0]
BM[1:0
]
(3)
Res.
Bank
[1:0]
Row[10:0] Column[8:0] BM[1:0
Res.
Bank
[1:0]
Row[10:0] Column[9:0] BM[1:0
Res.
Bank
[1:0]
Row[10:0] Column[10:0] BM[1:0
12-bit row size
configuration
Res.
Bank
[1:0]
Row[11:0] Column[7:0] BM[1:0
Res.
Bank
[1:0]
Row[11:0] Column[8:0] BM[1:0
Res.
Bank
[1:0]
Row[11:0] Column[9:0] BM[1:0
Res.
Bank
[1:0]
Row[11:0] Column[10:0] BM[1:0