ST STM32F405

Advanced-control timers (TIM1 and TIM8) RM0090
524/1749 RM0090 Rev 18
Figure 95. Counter timing diagram, internal clock divided by 1
Figure 96. Counter timing diagram, internal clock divided by 2
36 34
33
32 31
30 2F
04
03
02 01 00
05
MS31184V1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
(cnt_udf)
Update interrupt flag
(UIF)
35
MS31185V1
CK_PSC
CNT_EN
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag
(UIF)
0002
0001
0000
0036
0035
0034
0033