Serial peripheral interface (SPI) RM0090
904/1749 RM0090 Rev 18
Figure 270. MSB justified 16-bit or 32-bit full-accuracy length with CPOL = 0
Data are latched on the falling edge of CK (for transmitter) and are read on the rising edge
(for the receiver).
Figure 271. MSB justified 24-bit frame length with CPOL = 0
Figure 272. MSB justified 16-bit extended to 32-bit packet frame with CPOL = 0
LSB justified standard
This standard is similar to the MSB justified standard (no difference for the 16-bit and 32-bit
full-accuracy frame formats).
MS30100 V1
CK
WS
SD
Transmission
Reception
16- or 32 bit data
MSB
LSB
Channel left
Channel right
MSB
MS30101V1
CK
WS
SD
Transmission
Reception
24 bit data
MSB
LSB
Channel left 32-bit
Channel right
8-bit remaining
0 forced
MS30102V1
CK
WS
SD
Transmission
Reception
16-bit data
MSB LSB
Channel left 32-bit
Channel right
16-bit remaining
0 forced
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