ST STM32F405 User Manual

Interrupts and events RM0090
372/1749 RM0090 Rev 18
Table 61. Vector table for STM32F405xx/07xx and STM32F415xx/17xx
Position
Priority
Type of
priority
Acronym Description Address
- - - Reserved 0x0000 0000
-3 fixed Reset Reset 0x0000 0004
-2 fixed NMI
Non maskable interrupt. The RCC
Clock Security System (CSS) is linked
to the NMI vector.
0x0000 0008
-1 fixed HardFault All class of fault 0x0000 000C
0 settable MemManage Memory management 0x0000 0010
1 settable BusFault Pre-fetch fault, memory access fault 0x0000 0014
2 settable UsageFault Undefined instruction or illegal state 0x0000 0018
- - - Reserved
0x0000 001C - 0x0000
002B
3 settable SVCall
System service call via SWI
instruction
0x0000 002C
4 settable Debug Monitor Debug Monitor 0x0000 0030
- - - Reserved 0x0000 0034
5 settable PendSV Pendable request for system service 0x0000 0038
6 settable SysTick System tick timer 0x0000 003C
0 7 settable WWDG Window Watchdog interrupt 0x0000 0040
1 8 settable PVD
PVD through EXTI line detection
interrupt
0x0000 0044
2 9 settable TAMP_STAMP
Tamper and TimeStamp interrupts
through the EXTI line
0x0000 0048
3 10 settable RTC_WKUP
RTC Wakeup interrupt through the
EXTI line
0x0000 004C
4 11 settable FLASH Flash global interrupt 0x0000 0050
5 12 settable RCC RCC global interrupt 0x0000 0054
6 13 settable EXTI0 EXTI Line0 interrupt 0x0000 0058
7 14 settable EXTI1 EXTI Line1 interrupt 0x0000 005C
8 15 settable EXTI2 EXTI Line2 interrupt 0x0000 0060
9 16 settable EXTI3 EXTI Line3 interrupt 0x0000 0064
10 17 settable EXTI4 EXTI Line4 interrupt 0x0000 0068
11 18 settable DMA1_Stream0 DMA1 Stream0 global interrupt 0x0000 006C

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English