Cryptographic processor (CRYP) RM0090
722/1749 RM0090 Rev 18
23.3 CRYP functional description
The cryptographic processor implements a Triple-DES (TDES, that also supports DES) core
and an AES cryptographic core. Section 23.3.1 and Section 23.3.2 provide details on these
cores.
Since the TDES and the AES algorithms use block ciphers, incomplete input data blocks
have to be padded prior to encryption (extra bits should be appended to the trailing end of
the data string). After decryption, the padding has to be discarded. The hardware does not
manage the padding operation, the software has to handle it.
Figure 216 shows the block diagram of the cryptographic processor.
Figure 216. Block diagram (STM32F415/417xx)
32-bit AHB2 bus
Processor core
DES/TDES/AES
CRYP_DIN
swappi ng
swappin g
8 × 32-bit
IN FIFO
8 × 32-bit
OUT FIFO
CRYP_CR
CRYP_K0. ..K3
CRYP_IV0...IV1
IV0...IV127
k255...k0
CRYP_IMSCR
CRYP_RIS
CRYP_MISR
CRYP_DMACR
CRYP_SR
Status
DMA control register
Interrupt registers
Control register
Initialization vectors
Key
ai16068b
CRYP_DOUT
To Next Page
Loading...
Need help?
General
