RM0090 Rev 18 715/1749
RM0090 Window watchdog (WWDG)
719
In some applications, the EWI interrupt can be used to manage a software system check
and/or system recovery/graceful degradation, without generating a WWDG reset. In this
case, the corresponding interrupt service routine (ISR) should reload the WWDG counter to
avoid the WWDG reset, then trigger the required actions.
The EWI interrupt is cleared by writing '0' to the EWIF bit in the WWDG_SR register.
Note: When the EWI interrupt cannot be served, e.g. due to a system lock in a higher priority task,
the WWDG reset will eventually be generated.
22.4 How to program the watchdog timeout
Warning: When writing to the WWDG_CR register, always write 1 in the
T6 bit to avoid generating an immediate reset.
Figure 215. Window watchdog timing diagram
The formula to calculate the WWDG timeout value is given by:
where:
t
WWDG
: WWDG timeout
t
PCLK1
: APB1 clock period measured in ms
4096: value corresponding to internal divider
ai17101c
W[6:0]
T[6:0] CNT downcounter
Refresh not allowed
0x3F
Refresh allowed
Time
T6 bit
RESET
t
WWDG
t
PCLK1
4096× 2
WDGTB[1:0]
× T[5:0] 1+()×= ms()
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