Flexible memory controller (FMC) RM0090
1630/1749 RM0090 Rev 18
3-2 MTYP[1:0] As needed
1 MUXEN 0x0
0 MBKEN 0x1
Table 281. FMC_BTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x3
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for
read accesses.
7-4 ADDHLD
Duration of the middle phase of the read access (ADDHLD HCLK
cycles)
3-0 ADDSET[3:0]
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses. Minimum value for ADDSET is 1.
Table 282. FMC_BWTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x3
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST + 1 HCLK cycles) for
write accesses.
7-4 ADDHLD
Duration of the middle phase of the write access (ADDHLD HCLK
cycles)
3-0 ADDSET[3:0]
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 1.
Table 280. FMC_BCRx bit fields (continued)
Bit No. Bit name Value to set
To Next Page
Loading...
Need help?
General
