ST STM32F405

RM0090 Rev 18 601/1749
RM0090 General-purpose timers (TIM2 to TIM5)
649
Figure 152. Counter timing diagram, Update event with ARPE=1 (counter underflow)
Figure 153. Counter timing diagram, Update event with ARPE=1 (counter overflow)
MS37360V1
FD 36
CK_INT
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter underflow
Update interrupt flag (UIF)
00 02 03 04 05 06 0701
CNT_EN
Auto-reload preload register
Write a new value in TIMx_ARR
06 05 04 03 02 01
FD 36
Auto-reload active register
MS37361V1
FD 36
CK_INT
Timer clock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
36 34 33 32 31 30 2FF8 F9 FA FB FCF7 35
CNT_EN
Auto-reload preload register
Write a new value in TIMx_ARR
Auto-reload active register
FD 36