ST STM32F405 User Manual

USB on-the-go full-speed (OTG_FS) RM0090
1270/1749 RM0090 Rev 18
Power and clock gating CSR map
There is a single register for power and clock gating. It is available in both host and device
modes.
... ... ...
Device IN Endpoint x
(1)
/Host OUT Channel x
(1)
: DFIFO Write Access
Device OUT Endpoint x
(1)
/Host IN Channel x
(1)
: DFIFO Read Access
0xX000–0xXFFC
w
r
1. Where x is 3 in device mode and 7 in host mode.
Table 202. Power and clock gating control and status registers
Register name Acronym Offset address: 0xE00–0xFFF
Power and clock gating control register OTG_FS_PCGCCTL 0xE00-0xE04
Reserved - 0xE05–0xFFF
Table 201. Data FIFO (DFIFO) access register map (continued)
FIFO access register section Address range Access

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English