Flexible memory controller (FMC) RM0090
1628/1749 RM0090 Rev 18
Mode D - asynchronous access with extended address
Figure 467. ModeD read access waveforms
Table 279. FMC_BWTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x2
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for
write accesses.
7-4 ADDHLD Don’t care
3-0 ADDSET[3:0]
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses. Minimum value for ADDSET is 0.
A[25:0]
NOE
ADDSET DATAST
Memory transaction
NEx
D[31:0]
HCLK cycles HCLK cycles
NWE
NADV
data driven
by memory
MS30461V1
High
ADDHLD
HCLK cycles
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