ST STM32F405 User Manual

Reset and clock control for STM32F42xxx and STM32F43xxx (RCC) RM0090
152/1749 RM0090 Rev 18
Each clock source can be switched on or off independently when it is not used, to optimize
power consumption.
Figure 16. Clock tree
1. For full details about the internal and external clock source characteristics, refer to the Electrical characteristics section in
the device datasheet.
2. When TIMPRE bit of the RCC_DCKCFGR register is reset, if APBx prescaler is 1, then TIMxCLK = PCLKx, otherwise
TIMxCLK = 2x PCLKx.
3. When TIMPRE bit in the RCC_DCKCFGR register is set, if APBx prescaler is 1,2 or 4, then TIMxCLK = HCLK, otherwise
TIMxCLK = 4x PCLKx.
MS30434V2
PLL
MII_RMII_SEL in SYSCFG_PMC to Ethernet MAC
LSE
ETH_MII_TX_CLK_MII
OTG_HS_ULPI_CK
PLLI2SCLK
FCLK Cortex
free-running clock
APBx peripheral clocks
48 MHz
clocks
USBHS
ULPI clock
Ethernet
PTP clock
MCO1
MCO2
ETH_MII_RX_CLK_MI
I
OSC32_IN
OSC32_OUT
To Independent
watchdog
LSE
LSI
to RTC
RTCCLK
RTCSEL[1:0]
IWDGCLK
OSC_IN
OSC_OUT
PLLCLK
HSI
HSI
HSE
SW
SYSCLK
180 MHz
max
HCLK
to AHB bus, core,
memory and DMA
180 MHz max.
to Cortex System timer
Clock
enable
PLL48CK
I2S clocks
AHB
PRESC
/1,2,..512
MACRMIICLK
MACTXCLK
MACRXCLK
Watchdog
enable
RTC
enable
Peripheral
clock enable
/2 to 31
PLLI2S
SYSCLK
Ext. clock
I2SSRC
HSE_RTC
HSE
I2S_CKIN
PHY Ethernet
25 to 50 MHz
USB2.0 PHY
24 to 60 MHz
PLLSAI
PLLSAICLK
PLLLCDCLK
PLLSAICLK
SAI1_A clock
SAI1_B clock
LCD-TFT
clock
LSI RC
32 kHz
LSE OSC
32.768 kHz
/1 to 5
/1 to 5
16 MHz
HSI RC
4-26 MHz
HSE OSC
VCO
xN
/P
/Q
/R
/M
VCO
xN
/P
/Q
/R
DIV
DIV
DIV
VCO
xN
/P
/Q
/R
/2,20
Peripheral
clock enable
Peripheral
clock enable
Peripheral
clock enable
Peripheral
clock enable
Peripheral
clock enable
Peripheral
clock enable
Peripheral
clock enable
Peripheral
clock enable
Peripheral
clock enable
/8
APBx
PRESC
/1,2,4,8,16
APBx timer clocks
if (APBx presc =
1x1 else x2
Peripheral clock
enable
Peripheral clock
enable

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English