ST STM32F405 - Figure 102. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0 X36; Figure 103. Counter Timing Diagram, Internal Clock Divided by N

Advanced-control timers (TIM1 and TIM8) RM0090
528/1749 RM0090 Rev 18
Figure 102. Counter timing diagram, internal clock divided by 4, TIMx_ARR=0x36
1. Center-aligned mode 2 or 3 is used with an UIF on overflow.
Figure 103. Counter timing diagram, internal clock divided by N
0034 0035
MS31191V2
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Counter overflow
Update interrupt flag (UIF)
CNT_EN
0036 0035
MS31192V2
CK_PSC
Timerclock = CK_CNT
Counter register
Update event (UEV)
Update interrupt flag (UIF)
Counter underflow
001F20 01