Flexible static memory controller (FSMC) RM0090
1574/1749 RM0090 Rev 18
3-2 MTYP[0:1] 0x1 or 0x2
1 MUXEN As needed
0 MBKEN 0x1
Table 243. FSMC_BTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29:28 ACCMOD 0x0
27-24 DATLAT Data latency
23-20 CLKDIV
0x0 to get CLK = HCLK (not supported)
0x1 to get CLK = 2 × HCLK
..
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST Don’t care
7-4 ADDHLD Don’t care
3-0 ADDSET[3:0] Don’t care
Table 242. FSMC_BCRx bit fields (continued)
Bit No. Bit name Value to set
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