ST STM32F405 User Manual

RM0090 Rev 18 1561/1749
RM0090 Flexible static memory controller (FSMC)
1601
Note: The FSMC_BWTRx register is valid only if extended mode is set (mode B), otherwise all its
content is don’t care.
3-2 MTYP[0:1] 0x2 (NOR Flash memory)
1 MUXEN 0x0
0 MBKEN 0x1
Table 232. FSMC_BTRx bit fields
Bit
number
Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x1
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST HCLK cycles) for
read accesses.
7-4 ADDHLD Don’t care
3-0 ADDSET[3:0]
Duration of the first access phase (ADDSET HCLK cycles) for read
accesses.
Minimum value for ADDSET is 0.
Table 233. FSMC_BWTRx bit fields
Bit
number
Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x1
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST+1 HCLK cycles for
write accesses,
7-4 ADDHLD Don’t care
3-0 ADDSET[3:0]
Duration of the first access phase (ADDSET HCLK cycles) for write
accesses.
Minimum value for ADDSET is 0.
Table 231. FSMC_BCRx bit fields (continued)
Bit
number
Bit name Value to set

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English