RM0090 Rev 18 1575/1749
RM0090 Flexible static memory controller (FSMC)
1601
Figure 453. Synchronous multiplexed write mode - PSRAM (CRAM)
1. Memory must issue NWAIT signal one cycle in advance, accordingly WAITCFG must be programmed to 0.
2. NWAIT polarity is set to 0.
3. Byte Lane (NBL) outputs are not shown, they are held low while NEx is active.
Addr[15:0] data
addr[25:16]
Memory transaction = burst of 2 half words
HCLK
CLK
A[25:16]
NEx
NOE
NWE
Hi-Z
NADV
NWAIT
(WAITCFG = 0)
A/D[15:0]
1 clock 1 clock
(DATLAT + 2)
inserted wait state
ai14731f
CLK cycles
data
Table 244. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-20 Reserved 0x000
19 CBURSTRW 0x1
18-16 CPSIZE As needed (0x1 for CRAM 1.5)
15 ASCYCWAIT 0x0
14 EXTMOD 0x0
13 WAITEN Set to 1 if the memory supports this feature, otherwise keep at 0.
12 WREN 0x1
11 WAITCFG 0x0
10 WRAPMOD 0x0
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