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ST STM32F405 User Manual
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RM0090 Rev 18
773/1749
RM0090
Hash processo
r (HASH)
797
25.3 HASH
functional
description
Figure
1
shows the block diagram of the hash processor
.
Figure 233. Block diagram for STM32F415/41
7xx
32-bit AHB2 bus
Has
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/
HMAC
SHA
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M
D
5
HASH_DIN
swa
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16 × 32-bit
IN FIFO
HASH_CR
HAS
H_H0...H4
HAS
H_CSR0..50
co
n
text
diges
t
HAS
H_IM
R
HAS
H_S
R
Interrupt registers
Control register
Context swapping
Message digest
processor
core
HASH_ST
R
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tart register
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F
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AS
H
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Control and status
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Data
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774
Table of Contents
Table of Contents
2
List of Tables
40
Documentation Conventions
57
List of Abbreviations for Registers
57
Glossary
58
Peripheral Availability
58
Memory and Bus Architecture
59
System Architecture
59
Figure 1. System Architecture for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx Devices
60
D-Bus
62
Figure 2. System Architecture for Stm32F42Xxx and Stm32F43Xxx Devices
62
I-Bus
62
S-Bus
62
Busmatrix
63
DMA Memory Bus
63
DMA Peripheral Bus
63
DMA2D Bus
63
Ethernet DMA Bus
63
LCD-TFT Controller DMA Bus
63
USB OTG HS DMA Bus
63
AHB/APB Bridges (APB)
64
Memory Map
64
Memory Organization
64
Table 1
64
Table 1. Stm32F4Xx Register Boundary Addresses
64
Bit Banding
68
Embedded SRAM
68
Flash Memory Overview
68
Boot Configuration
69
Table 2. Boot Modes
69
Table 3. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
71
Table 4. Memory Mapping Vs. Boot Mode/Physical Remap in Stm32F42Xxx and Stm32F43Xxx
71
Embedded Flash Memory Interface
73
Figure 3. Flash Memory Interface Connection Inside System Architecture (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
73
Introduction
73
Main Features
73
Embedded Flash Memory in Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
74
Figure 4. Flash Memory Interface Connection Inside System Architecture (Stm32F42Xxx and Stm32F43Xxx)
74
Table 5. Flash Module Organization (Stm32F40X and Stm32F41X)
75
Embedded Flash Memory in Stm32F42Xxx and Stm32F43Xxx
76
Table 6. Flash Module - 2 Mbyte Dual Bank Organization (Stm32F42Xxx and Stm32F43Xxx)
77
Mbyte Flash Memory Single Bank Vs Dual Bank Organization (Stm32F42Xxx and Stm32F43Xxx)
78
Mbyte Single Bank Flash Memory Organization (Stm32F42Xxx and Stm32F43Xxx)
78
Table 9. 1 Mbyte Dual Bank Flash Memory Organization (Stm32F42Xxx and Stm32F43Xxx)
79
Read Interface
80
Relation between CPU Clock Frequency and Flash Memory Read Time
80
Table 10. Number of Wait States According to CPU Clock (HCLK) Frequency (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
80
Table 11. Number of Wait States According to CPU Clock (HCLK) Frequency (Stm32F42Xxx and Stm32F43Xxx)
81
Adaptive Real-Time Memory Accelerator (ART Accelerator™)
82
Figure 5. Sequential 32-Bit Instruction Execution
83
Erase and Program Operations
84
Unlocking the Flash Control Register
84
Erase
85
Program/Erase Parallelism
85
Table 12. Program/Erase Parallelism
85
Programming
86
Read-While-Write (RWW)
87
Description of User Option Bytes
88
Interrupts
88
Option Bytes
88
Table 13. Flash Interrupt Request
88
Table 14. Option Byte Organization
88
Table 15. Description of the Option Bytes (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
89
Table 16. Description of the Option Bytes (Stm32F42Xxx and Stm32F43Xxx)
90
Programming User Option Bytes
92
Read Protection (RDP)
93
Figure 6. RDP Levels
94
Table 17. Access Versus Read Protection Level
94
Write Protections
94
Proprietary Code Readout Protection (PCROP)
95
Figure 7. PCROP Levels
96
One-Time Programmable Bytes
97
Table 18. OTP Area Organization
97
Flash Access Control Register (FLASH_ACR)
98
Flash Interface Registers
98
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
98
Flash Access Control Register (FLASH_ACR)
99
For Stm32F42Xxx and Stm32F43Xxx
99
Flash Key Register (FLASH_KEYR)
100
Flash Option Key Register (FLASH_OPTKEYR)
100
Flash Status Register (FLASH_SR) for
101
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
101
Stm32F42Xxx and Stm32F43Xxx
102
Flash Control Register (FLASH_CR) for
103
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
103
Flash Control Register (FLASH_CR) for
105
Stm32F42Xxx and Stm32F43Xxx
105
Flash Option Control Register (FLASH_OPTCR) for
106
Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
106
Flash Option Control Register (FLASH_OPTCR)
108
For Stm32F42Xxx and Stm32F43Xxx
108
Flash Option Control Register (FLASH_OPTCR1)
110
For Stm32F42Xxx and Stm32F43Xxx
110
Flash Interface Register Map
111
Table 19. Flash Register Map and Reset Values (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
111
Table 20. Flash Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)
111
CRC Calculation Unit
113
CRC Introduction
113
CRC Main Features
113
Figure 8. CRC Calculation Unit Block Diagram
113
CRC Functional Description
114
CRC Registers
114
Data Register (CRC_DR)
114
Independent Data Register (CRC_IDR)
114
Control Register (CRC_CR)
115
CRC Register Map
115
Table 21. CRC Calculation Unit Register Map and Reset Values
115
Figure 9. Power Supply Overview for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
116
Power Controller (PWR)
116
Power Supplies
116
Figure 10. Power Supply Overview for Stm32F42Xxx and Stm32F43Xxx
117
Independent A/D Converter Supply and Reference Voltage
117
Battery Backup Domain
118
Figure 11. Backup Domain
120
Voltage Regulator for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
120
Voltage Regulator for Stm32F42Xxx and Stm32F43Xxx
121
Table 22. Voltage Regulator Configuration Mode Versus Device Operating Mode
122
Figure 12. Power-On Reset/Power-Down Reset Waveform
124
Power Supply Supervisor
124
Power-On Reset (Por)/Power-Down Reset (PDR)
124
Brownout Reset (BOR)
125
Figure 13. BOR Thresholds
125
Programmable Voltage Detector (PVD)
125
Figure 14. PVD Thresholds
126
Low-Power Modes
126
Peripheral Clock Gating
128
Slowing down System Clocks
128
Table 23. Low-Power Mode Summary
128
Sleep Mode
129
Table 24. Sleep-Now Entry and Exit
129
Stop Mode (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
130
Table 25. Sleep-On-Exit Entry and Exit
130
Table 26. Stop Operating Modes (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
131
Table 27. Stop Mode Entry and Exit (for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
132
Stop Mode (Stm32F42Xxx and Stm32F43Xxx)
133
Table 28. Stop Operating Modes (Stm32F42Xxx and Stm32F43Xxx)
134
Standby Mode
136
Table 29. Stop Mode Entry and Exit (Stm32F42Xxx and Stm32F43Xxx)
136
Table 30. Standby Mode Entry and Exit
137
Programming the RTC Alternate Functions to Wake up the Device from the Stop and Standby Modes
138
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
141
Power Control Registers (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
141
PWR Power Control Register (PWR_CR)
141
For Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
142
PWR Power Control/Status Register (PWR_CSR)
142
For Stm32F42Xxx and Stm32F43Xxx
144
Power Control Registers (Stm32F42Xxx and Stm32F43Xxx)
144
PWR Power Control Register (PWR_CR)
144
For Stm32F42Xxx and Stm32F43Xxx
147
PWR Power Control/Status Register (PWR_CSR)
147
PWR Register Map
149
Table 31. PWR - Register Map and Reset Values for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
149
Table 32. PWR - Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx
149
Power Reset
150
Reset
150
Reset and Clock Control for Stm32F42Xxx and Stm32F43Xxx (RCC)
150
System Reset
150
Backup Domain Reset
151
Clocks
151
Figure 15. Simplified Diagram of the Reset Circuit
151
Figure 16. Clock Tree
152
Figure 17. HSE/ LSE Clock Sources
154
HSE Clock
154
HSI Clock
155
PLL Configuration
155
LSE Clock
156
LSI Clock
156
System Clock (SYSCLK) Selection
156
Clock Security System (CSS)
157
RTC/AWU Clock
157
Clock-Out Capability
158
Internal/External Clock Measurement Using TIM5/TIM11
158
Watchdog Clock
158
Figure 18. Frequency Measurement with TIM5 in Input Capture Mode
159
Figure 19. Frequency Measurement with TIM11 in Input Capture Mode
160
RCC Clock Control Register (RCC_CR)
161
RCC Registers
161
RCC PLL Configuration Register (RCC_PLLCFGR)
163
RCC Clock Configuration Register (RCC_CFGR)
165
RCC Clock Interrupt Register (RCC_CIR)
167
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
170
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
173
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
174
RCC APB1 Peripheral Reset Register (RCC_APB1RSTR)
174
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
178
RCC AHB1 Peripheral Clock Register (RCC_AHB1ENR)
180
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
182
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
183
RCC APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
183
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
187
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB1LPENR)
189
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)
192
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)
193
RCC APB1 Peripheral Clock Enable in Low Power Mode Register (RCC_APB1LPENR)
193
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register (RCC_APB2LPENR)
197
RCC Backup Domain Control Register (RCC_BDCR)
199
RCC Clock Control & Status Register (RCC_CSR)
200
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
202
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
203
RCC PLL Configuration Register (RCC_PLLSAICFGR)
206
RCC Dedicated Clock Configuration Register (RCC_DCKCFGR)
207
RCC Register Map
210
Table 33. RCC Register Map and Reset Values for Stm32F42Xxx and Stm32F43Xxx
210
Reset
213
Reset and Clock Control for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx(RCC)
213
System Reset
213
Backup Domain Reset
214
Figure 20. Simplified Diagram of the Reset Circuit
214
Power Reset
214
Clocks
215
Figure 21. Clock Tree
216
HSE Clock
217
Figure 22. HSE/ LSE Clock Sources
218
HSI Clock
218
LSE Clock
219
PLL Configuration
219
Clock Security System (CSS)
220
LSI Clock
220
System Clock (SYSCLK) Selection
220
RTC/AWU Clock
221
Watchdog Clock
221
Clock-Out Capability
222
Internal/External Clock Measurement Using TIM5/TIM11
222
Figure 23. Frequency Measurement with TIM5 in Input Capture Mode
223
Figure 24. Frequency Measurement with TIM11 in Input Capture Mode
223
RCC Clock Control Register (RCC_CR)
224
RCC Registers
224
RCC PLL Configuration Register (RCC_PLLCFGR)
226
RCC Clock Configuration Register (RCC_CFGR)
228
RCC Clock Interrupt Register (RCC_CIR)
230
RCC AHB1 Peripheral Reset Register (RCC_AHB1RSTR)
233
RCC AHB2 Peripheral Reset Register (RCC_AHB2RSTR)
236
RCC AHB3 Peripheral Reset Register (RCC_AHB3RSTR)
237
RCC APB1 Peripheral Reset Register (RCC_APB1RSTR)
237
RCC APB2 Peripheral Reset Register (RCC_APB2RSTR)
240
RCC AHB1 Peripheral Clock Enable Register (RCC_AHB1ENR)
242
RCC AHB2 Peripheral Clock Enable Register (RCC_AHB2ENR)
244
RCC AHB3 Peripheral Clock Enable Register (RCC_AHB3ENR)
245
RCC APB1 Peripheral Clock Enable Register (RCC_APB1ENR)
245
RCC APB2 Peripheral Clock Enable Register (RCC_APB2ENR)
248
RCC AHB1 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB1LPENR)
250
RCC AHB2 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB2LPENR)
252
RCC AHB3 Peripheral Clock Enable in Low Power Mode Register (RCC_AHB3LPENR)
253
RCC APB1 Peripheral Clock Enable in Low Power Mode Register (RCC_APB1LPENR)
254
RCC APB2 Peripheral Clock Enabled in Low Power Mode Register (RCC_APB2LPENR)
257
RCC Backup Domain Control Register (RCC_BDCR)
259
RCC Clock Control & Status Register (RCC_CSR)
260
RCC Spread Spectrum Clock Generation Register (RCC_SSCGR)
262
RCC PLLI2S Configuration Register (RCC_PLLI2SCFGR)
263
RCC Register Map
265
Table 34. RCC Register Map and Reset Values
265
General-Purpose I/Os (GPIO)
267
GPIO Functional Description
267
GPIO Introduction
267
GPIO Main Features
267
Figure 25. Basic Structure of a Five-Volt Tolerant I/O Port Bit
268
Table 35. Port Bit Configuration Table
268
General-Purpose I/O (GPIO)
269
I/O Pin Multiplexer and Mapping
270
Table 36. Flexible SWJ-DP Pin Assignment
271
Figure 26. Selecting an Alternate Function on Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
272
Figure 27. Selecting an Alternate Function on Stm32F42Xxx and Stm32F43Xxx
273
GPIO Locking Mechanism
274
I/O Data Bitwise Handling
274
I/O Port Control Registers
274
I/O Port Data Registers
274
External Interrupt/Wakeup Lines
275
I/O Alternate Function Input/Output
275
Input Configuration
275
Figure 28. Input Floating/Pull Up/Pull down Configurations
276
Output Configuration
276
Alternate Function Configuration
277
Figure 29. Output Configuration
277
Figure 30. Alternate Function Configuration
277
Analog Configuration
278
Figure 31. High Impedance-Analog Configuration
278
Port Pins
278
Using the OSC32_IN/OSC32_OUT Pins as GPIO PC14/PC15
278
Using the OSC_IN/OSC_OUT Pins as GPIO PH0/PH1 Port Pins
278
Selection of RTC_AF1 and RTC_AF2 Alternate Functions
279
Table 38. RTC_AF2 Pin
280
(X = a
281
GPIO Port Mode Register (Gpiox_Moder) (X = A..I/J/K
281
GPIO Port Output Type Register (Gpiox_Otyper)
281
GPIO Registers
281
(X = a
282
GPIO Port Input Data Register (Gpiox_Idr) (X = a
283
GPIO Port Output Data Register (Gpiox_Odr) (X = a
283
(X = a
284
GPIO Port Bit Set/Reset Register (Gpiox_Bsrr) (X = a
284
GPIO Alternate Function Low Register (Gpiox_Afrl) (X = a
285
(X = a
286
GPIO Register Map
287
Table 39. GPIO Register Map and Reset Values
287
I/O Compensation Cell
289
SYSCFG Memory Remap Register (SYSCFG_MEMRMP)
289
SYSCFG Registers for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
289
System Configuration Controller (SYSCFG)
289
SYSCFG Peripheral Mode Configuration Register (SYSCFG_PMC)
290
(Syscfg_Exticr1)
291
(Syscfg_Exticr2)
291
SYSCFG External Interrupt Configuration Register 1
291
(Syscfg_Exticr3)
292
SYSCFG External Interrupt Configuration Register 3
292
(Syscfg_Exticr4)
293
SYSCFG External Interrupt Configuration Register 4
293
Table 40. SYSCFG Register Map and Reset Values (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
294
Table 41. SYSCFG Register Map and Reset Values (Stm32F42Xxx and Stm32F43Xxx)
301
Figure 32. DMA Block Diagram
304
Figure 33. System Implementation of the Two DMA Controllers (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
305
Figure 34. System Implementation of the Two DMA Controllers (Stm32F42Xxx and Stm32F43Xxx)
306
Figure 35. Channel Selection
307
Table 42. DMA1 Request Mapping
307
Table 43. DMA2 Request Mapping
308
Table 44. Source and Destination Address
309
Figure 36. Peripheral-To-Memory Mode
310
Figure 37. Memory-To-Peripheral Mode
311
Figure 38. Memory-To-Memory Mode
312
Table 45. Source and Destination Address Registers in Double Buffer Mode (DBM=1)
314
Table 46. Packing/Unpacking & Endian Behavior (Bit PINC = MINC = 1)
315
Table 47. Restriction on NDT Versus PSIZE and MSIZE
316
Figure 39. FIFO Structure
317
Table 48. FIFO Threshold Configurations
318
Table 49. Possible DMA Configurations
322
Table 50. DMA Interrupt Requests
324
Table 51. DMA Register Map and Reset Values
335
Table 52. Supported Color Mode in Input
342
Table 53. Data Order in Memory
343
Table 56. CLUT Data Order in Memory
345
Table 57. Supported Color Mode in Output
346
Table 58. Data Order in Memory
346
Table 59. DMA2D Interrupt Requests
351
Table 60. DMA2D Register Map and Reset Values
369
Table 61. Vector Table for Stm32F405Xx/07Xx and Stm32F415Xx/17Xx
372
Table 62. Vector Table for Stm32F42Xxx and Stm32F43Xxx
375
Figure 41. External Interrupt/Event Controller Block Diagram
380
Figure 42. External Interrupt/Event GPIO Mapping (Stm32F405Xx/07Xx and Stm32F415Xx/17Xx)
382
Figure 43. External Interrupt/Event GPIO Mapping (Stm32F42Xxx and Stm32F43Xxx)
383
Table 63. External Interrupt/Event Controller Register Map and Reset Values
387
Table 64. External Interrupt/Event Controller Register Map and Reset Values
387
Figure 44. Single ADC Block Diagram
389
Table 65. ADC Pins
390
Figure 45. Timing Diagram
392
Figure 46. Analog Watchdog's Guarded Area
393
Table 66. Analog Watchdog Channel Selection
393
Figure 47. Injected Conversion Latency
394
Figure 48. Right Alignment of 12-Bit Data
396
Figure 49. Left Alignment of 12-Bit Data
396
Figure 50. Left Alignment of 6-Bit Data
396
Table 67. Configuring the Trigger Polarity
397
Table 68. External Trigger for Regular Channels
398
Table 69. External Trigger for Injected Channels
399
Figure 52. Injected Simultaneous Mode on 4 Channels: Dual ADC Mode
405
Figure 53. Injected Simultaneous Mode on 4 Channels: Triple ADC Mode
405
Figure 54. Regular Simultaneous Mode on 16 Channels: Dual ADC Mode
406
Figure 55. Regular Simultaneous Mode on 16 Channels: Triple ADC Mode
406
Figure 56. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Dual ADC Mode
407
Figure 57. Interleaved Mode on 1 Channel in Continuous Conversion Mode: Triple ADC Mode
408
Figure 58. Alternate Trigger: Injected Group of each ADC
409
Figure 59. Alternate Trigger: 4 Injected Channels (each ADC) in Discontinuous Mode
410
Figure 60. Alternate Trigger: Injected Group of each ADC
410
Figure 61. Alternate + Regular Simultaneous
411
Figure 62. Case of Trigger Occurring During Injected Conversion
412
Figure 63. Temperature Sensor and VREFINT Channel Block Diagram
413
Table 70. ADC Interrupts
414
Table 71. ADC Global Register Map
430
Table 72. ADC Register Map and Reset Values for each ADC
431
Table 73. ADC Register Map and Reset Values (Common ADC Registers)
432
Figure 64. DAC Channel Block Diagram
434
Table 74. DAC Pins
434
Figure 65. Data Registers in Single DAC Channel Mode
436
Figure 66. Data Registers in Dual DAC Channel Mode
436
Figure 67. Timing Diagram for Conversion with Trigger Disabled TEN = 0
437
Table 75. External Triggers
437
Figure 68. DAC LFSR Register Calculation Algorithm
439
Figure 69. DAC Conversion (SW Trigger Enabled) with LFSR Wave Generation
439
Figure 70. DAC Triangle Wave Generation
440
Figure 71. DAC Conversion (SW Trigger Enabled) with Triangle Wave Generation
440
Table 76. DAC Register Map
453
Table 77. DCMI Pins
455
Figure 72. DCMI Block Diagram
456
Figure 73. Top-Level Block Diagram
457
Table 78. DCMI Signals
457
Figure 74. DCMI Signal Waveforms
458
Table 79. Positioning of Captured Data Bytes in 32-Bit Words (8-Bit Width)
458
Table 80. Positioning of Captured Data Bytes in 32-Bit Words (10-Bit Width)
458
Table 81. Positioning of Captured Data Bytes in 32-Bit Words (12-Bit Width)
459
Table 82. Positioning of Captured Data Bytes in 32-Bit Words (14-Bit Width)
459
Figure 75. Timing Diagram
460
Figure 76. Frame Capture Waveforms in Snapshot Mode
462
Figure 77. Frame Capture Waveforms in Continuous Grab Mode
463
Figure 78. Coordinates and Size of the Window after Cropping
464
Figure 79. Data Capture Waveforms
464
Figure 80. Pixel Raster Scan Order
465
Table 83. Data Storage in Monochrome Progressive Video Format
466
Table 84. Data Storage in RGB Progressive Video Format
466
Table 85. Data Storage in Ycbcr Progressive Video Format
467
Table 86. DCMI Interrupts
467
Table 87. DCMI Register Map and Reset Values
478
Figure 81. LTDC Block Diagram
481
Table 88. LTDC Registers Versus Clock Domain
482
Table 89. LCD-TFT Pins and Signal Interface
483
Figure 82. LCD-TFT Synchronous Timings
484
Figure 83. Layer Window Programmable Parameters
487
Table 90. Pixel Data Mapping Versus Color Format
487
Figure 84. Blending Two Layers with Background
490
Figure 85. Interrupt Events
491
Table 91. LTDC Interrupt Requests
491
Table 92. LTDC Register Map and Reset Values
512
Figure 86. Advanced-Control Timer Block Diagram
517
Figure 87. Counter Timing Diagram with Prescaler Division Change from 1 to 2
519
Figure 88. Counter Timing Diagram with Prescaler Division Change from 1 to 4
519
Figure 89. Counter Timing Diagram, Internal Clock Divided by 1
520
Figure 90. Counter Timing Diagram, Internal Clock Divided by 2
521
Figure 91. Counter Timing Diagram, Internal Clock Divided by 4
521
Figure 92. Counter Timing Diagram, Internal Clock Divided by N
521
Figure 93. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
522
Figure 94. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
522
Figure 95. Counter Timing Diagram, Internal Clock Divided by 1
524
Figure 96. Counter Timing Diagram, Internal Clock Divided by 2
524
Figure 97. Counter Timing Diagram, Internal Clock Divided by 4
525
Figure 98. Counter Timing Diagram, Internal Clock Divided by N
525
Figure 99. Counter Timing Diagram, Update Event When Repetition Counter Is Not Used
526
Figure 100. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr = 0X6
527
Figure 101. Counter Timing Diagram, Internal Clock Divided by 2
527
Figure 102. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
528
Figure 103. Counter Timing Diagram, Internal Clock Divided by N
528
Figure 104. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
529
Figure 105. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
529
Figure 106. Update Rate Examples Depending on Mode and Timx_Rcr Register Settings
531
Figure 107. Control Circuit in Normal Mode, Internal Clock Divided by 1
532
Figure 108. TI2 External Clock Connection Example
533
Figure 109. Control Circuit in External Clock Mode 1
534
Figure 110. External Trigger Input Block
534
Figure 111. Control Circuit in External Clock Mode 2
535
Figure 112. Capture/Compare Channel (Example: Channel 1 Input Stage)
536
Figure 113. Capture/Compare Channel 1 Main Circuit
536
Figure 114. Output Stage of Capture/Compare Channel (Channel 1 to 3)
537
Figure 115. Output Stage of Capture/Compare Channel (Channel 4)
537
Figure 116. PWM Input Mode Timing
539
Figure 117. Output Compare Mode, Toggle on OC1
541
Figure 118. Edge-Aligned PWM Waveforms (ARR=8)
542
Figure 119. Center-Aligned PWM Waveforms (ARR=8)
543
Figure 120. Complementary Output with Dead-Time Insertion
545
Figure 121. Dead-Time Waveforms with Delay Greater than the Negative Pulse
545
Figure 122. Dead-Time Waveforms with Delay Greater than the Positive Pulse
545
Figure 123. Output Behavior in Response to a Break
548
Figure 124. Clearing Timx Ocxref
549
Figure 125. 6-Step Generation, COM Example (OSSR=1)
550
Figure 126. Example of One Pulse Mode
551
Table 93. Counting Direction Versus Encoder Signals
553
Figure 127. Example of Counter Operation in Encoder Interface Mode
554
Figure 128. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
554
Figure 129. Example of Hall Sensor Interface
556
Figure 130. Control Circuit in Reset Mode
557
Figure 131. Control Circuit in Gated Mode
558
Figure 132. Control Circuit in Trigger Mode
559
Figure 133. Control Circuit in External Clock Mode 2 + Trigger Mode
560
Table 94. Timx Internal Trigger Connection
567
Break Feature
579
Table 95. Output Control Bits for Complementary Ocx and Ocxn Channels with
579
Table 96. TIM1 and TIM8 Register Map and Reset Values
587
Figure 134. General-Purpose Timer Block Diagram
590
Figure 135. Counter Timing Diagram with Prescaler Division Change from 1 to 2
592
Figure 136. Counter Timing Diagram with Prescaler Division Change from 1 to 4
592
Figure 137. Counter Timing Diagram, Internal Clock Divided by 1
593
Figure 138. Counter Timing Diagram, Internal Clock Divided by 2
593
Figure 139. Counter Timing Diagram, Internal Clock Divided by 4
594
Figure 140. Counter Timing Diagram, Internal Clock Divided by N
594
Figure 141. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
595
Figure 142. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
595
Figure 143. Counter Timing Diagram, Internal Clock Divided by 1
596
Figure 144. Counter Timing Diagram, Internal Clock Divided by 2
597
Figure 145. Counter Timing Diagram, Internal Clock Divided by 4
597
Figure 146. Counter Timing Diagram, Internal Clock Divided by N
597
Figure 147. Counter Timing Diagram, Update Event
598
Figure 148. Counter Timing Diagram, Internal Clock Divided by 1, Timx_Arr=0X6
599
Figure 149. Counter Timing Diagram, Internal Clock Divided by 2
599
Figure 150. Counter Timing Diagram, Internal Clock Divided by 4, Timx_Arr=0X36
600
Figure 151. Counter Timing Diagram, Internal Clock Divided by N
600
Figure 152. Counter Timing Diagram, Update Event with ARPE=1 (Counter Underflow)
601
Figure 153. Counter Timing Diagram, Update Event with ARPE=1 (Counter Overflow)
601
Figure 154. Control Circuit in Normal Mode, Internal Clock Divided by 1
602
Figure 155. TI2 External Clock Connection Example
603
Figure 156. Control Circuit in External Clock Mode 1
604
Figure 157. External Trigger Input Block
604
Figure 158. Control Circuit in External Clock Mode 2
605
Figure 159. Capture/Compare Channel (Example: Channel 1 Input Stage)
605
Figure 160. Capture/Compare Channel 1 Main Circuit
606
Figure 161. Output Stage of Capture/Compare Channel (Channel 1)
606
Figure 162. PWM Input Mode Timing
608
Figure 163. Output Compare Mode, Toggle on OC1
610
Figure 164. Edge-Aligned PWM Waveforms (ARR=8)
611
Figure 165. Center-Aligned PWM Waveforms (ARR=8)
612
Figure 166. Example of One-Pulse Mode
613
Figure 167. Clearing Timx Ocxref
615
Table 97. Counting Direction Versus Encoder Signals
616
Figure 168. Example of Counter Operation in Encoder Interface Mode
617
Figure 169. Example of Encoder Interface Mode with TI1FP1 Polarity Inverted
617
Figure 170. Control Circuit in Reset Mode
618
Figure 171. Control Circuit in Gated Mode
619
Figure 172. Control Circuit in Trigger Mode
620
Figure 173. Control Circuit in External Clock Mode 2 + Trigger Mode
621
Figure 174. Master/Slave Timer Example
621
Figure 175. Gating Timer 2 with OC1REF of Timer 1
622
Figure 176. Gating Timer 2 with Enable of Timer 1
623
Figure 177. Triggering Timer 2 with Update of Timer 1
624
Figure 178. Triggering Timer 2 with Enable of Timer 1
625
Figure 179. Triggering Timer 1 and 2 with Timer 1 TI1 Input
626
Table 98. Timx Internal Trigger Connection
632
Table 99. Output Control Bit for Standard Ocx Channels
641
Table 100. TIM2 to TIM5 Register Map and Reset Values
648
Figure 180. General-Purpose Timer Block Diagram (TIM9 and TIM12)
651
Figure 181. General-Purpose Timer Block Diagram (TIM10/11/13/14)
652
Figure 182. Counter Timing Diagram with Prescaler Division Change from 1 to 2
654
Figure 183. Counter Timing Diagram with Prescaler Division Change from 1 to 4
654
Figure 184. Counter Timing Diagram, Internal Clock Divided by 1
655
Figure 185. Counter Timing Diagram, Internal Clock Divided by 2
656
Figure 186. Counter Timing Diagram, Internal Clock Divided by 4
656
Figure 187. Counter Timing Diagram, Internal Clock Divided by N
656
Figure 188. Counter Timing Diagram, Update Event When ARPE=0 (Timx_Arr Not Preloaded)
657
Figure 189. Counter Timing Diagram, Update Event When ARPE=1 (Timx_Arr Preloaded)
657
Figure 190. Control Circuit in Normal Mode, Internal Clock Divided by 1
658
Figure 191. TI2 External Clock Connection Example
659
Figure 192. Control Circuit in External Clock Mode 1
659
Figure 193. Capture/Compare Channel (Example: Channel 1 Input Stage)
660
Figure 194. Capture/Compare Channel 1 Main Circuit
661
Figure 195. Output Stage of Capture/Compare Channel (Channel 1)
661
Figure 196. PWM Input Mode Timing
663
Figure 197. Output Compare Mode, Toggle on OC1
665
Figure 198. Edge-Aligned PWM Waveforms (ARR=8)
666
Figure 199. Example of One Pulse Mode
667
Figure 200. Control Circuit in Reset Mode
669
Figure 201. Control Circuit in Gated Mode
670
Figure 202. Control Circuit in Trigger Mode
670
Table 101. Timx Internal Trigger Connection
674
Table 102. Output Control Bit for Standard Ocx Channels
682
Table 103. TIM9/12 Register Map and Reset Values
684
Table 104. Output Control Bit for Standard Ocx Channels
691
Table 105. TIM10/11/13/14 Register Map and Reset Values
694
Figure 203. Basic Timer Block Diagram
696
Figure 204. Counter Timing Diagram with Prescaler Division Change from 1 to 2
698
Figure 205. Counter Timing Diagram with Prescaler Division Change from 1 to 4
698
Figure 206. Counter Timing Diagram, Internal Clock Divided by 1
699
Figure 207. Counter Timing Diagram, Internal Clock Divided by 2
700
Figure 208. Counter Timing Diagram, Internal Clock Divided by 4
700
Figure 209. Counter Timing Diagram, Internal Clock Divided by N
700
Preloaded)
701
Figure 212. Control Circuit in Normal Mode, Internal Clock Divided by 1
702
Table 106. TIM6 and TIM7 Register Map and Reset Values
707
Figure 213. Independent Watchdog Block Diagram
709
Table 107. Min/Max IWDG Timeout Period (in Ms) at 32 Khz (LSI)
709
Table 108. IWDG Register Map and Reset Values
712
Figure 214. Watchdog Block Diagram
714
Figure 215. Window Watchdog Timing Diagram
715
Table 109. Minimum and Maximum Timeout Values at 30 Mhz (F PCLK1 )
716
Table 110. WWDG Register Map and Reset Values
719
(Stm32F415/417Xx)
720
(Stm32F43Xxx)
720
Table 111. Number of Cycles Required to Process each 128-Bit Block
720
Figure 216. Block Diagram (Stm32F415/417Xx)
722
Figure 217. Block Diagram (Stm32F43Xxx)
723
Figure 218. DES/TDES-ECB Mode Encryption
725
Figure 219. DES/TDES-ECB Mode Decryption
725
Figure 220. DES/TDES-CBC Mode Encryption
727
Figure 221. DES/TDES-CBC Mode Decryption
728
Figure 222. AES-ECB Mode Encryption
729
Figure 223. AES-ECB Mode Decryption
730
Figure 224. AES-CBC Mode Encryption
731
Figure 225. AES-CBC Mode Decryption
732
Figure 226. AES-CTR Mode Encryption
733
Figure 227. AES-CTR Mode Decryption
734
Figure 228. Initial Counter Block Structure for the Counter Mode
734
Table 113. Data Types
740
Figure 229. 64-Bit Block Construction According to DATATYPE
741
Figure 230. Initialization Vectors Use in the TDES-CBC Encryption
743
Figure 231. CRYP Interrupt Mapping Diagram
748
Table 114. CRYP Register Map and Reset Values for Stm32F415/417Xx
763
Table 115. CRYP Register Map and Reset Values for Stm32F43Xxx
764
Figure 232. Block Diagram
767
Table 116. RNG Register Map and Reset Map
771
Figure 233. Block Diagram for Stm32F415/417Xx
773
Figure 234. Block Diagram for Stm32F43Xxx
774
Figure 235. Bit, Byte and Half-Word Swapping
776
Figure 236. HASH Interrupt Mapping Diagram
782
Table 117. HASH Register Map and Reset Values on Stm32F415/417Xx
795
Table 118. HASH Register Map and Reset Values on Stm32F43Xxx
796
Table 119. Effect of Low-Power Modes on RTC
814
Table 120. Interrupt Control Bits
815
Table 121. RTC Register Map and Reset Values
836
Figure 238. I2C Bus Protocol
841
Figure 239. I2C Block Diagram for Stm32F40X/41X
842
Figure 240. I2C Block Diagram for Stm32F42X/43X
843
Figure 241. Transfer Sequence Diagram for Slave Transmitter
845
Figure 242. Transfer Sequence Diagram for Slave Receiver
846
Figure 243. Transfer Sequence Diagram for Master Transmitter
849
Figure 244. Transfer Sequence Diagram for Master Receiver
850
Table 122. Maximum DNF[3:0] Value to be Compliant with Thd:dat(Max)
852
Table 123. Smbus Vs. I2C
854
Table 124. I2C Interrupt Requests
858
Figure 245. I2C Interrupt Mapping Diagram
859
Table 125. I2C Register Map and Reset Values
872
Figure 246. SPI Block Diagram
876
Figure 247. Single Master/ Single Slave Application
877
Figure 248. Data Clock Timing Diagram
879
Figure 249. TI Mode - Slave Mode, Single Transfer
881
Figure 250. TI Mode - Slave Mode, Continuous Transfer
882
Figure 251. TI Mode - Master Mode, Single Transfer
883
Figure 252. TI Mode - Master Mode, Continuous Transfer
884
Figure 253. TXE/RXNE/BSY Behavior in Master / Full-Duplex Mode
887
RXONLY=0) in Case of Continuous Transfers
887
Figure 254. TXE/RXNE/BSY Behavior in Slave / Full-Duplex Mode
888
RXONLY=0) in Case of Continuous Transfers
888
Continuous Transfers
889
Figure 255. TXE/BSY Behavior in Master Transmit-Only Mode (BIDIMODE=0 and RXONLY=0)
889
Figure 256. TXE/BSY in Slave Transmit-Only Mode (BIDIMODE=0 and RXONLY=0) in Case of
889
In Case of Continuous Transfers
889
Figure 257. RXNE Behavior in Receive-Only Mode (BIDIRMODE=0 and RXONLY=1)
890
In Case of Continuous Transfers
890
Figure 258. TXE/BSY Behavior When Transmitting (BIDIRMODE=0 and RXONLY=0)
891
In Case of Discontinuous Transfers
891
Figure 259. Transmission Using DMA
896
Figure 260. Reception Using DMA
896
Figure 261. TI Mode Frame Format Error Detection
898
Table 126. SPI Interrupt Requests
898
Figure 262. I
899
Figure 263. I2S Full Duplex Block Diagram
900
Figure 264. I 2 S Philips Protocol Waveforms (16/32-Bit Full Accuracy, CPOL = 0)
902
Figure 265. I 2 S Philips Standard Waveforms (24-Bit Frame with CPOL = 0)
902
Figure 266. Transmitting 0X8Eaa33
902
Figure 267. Receiving 0X8Eaa33
903
Figure 268. I
903
Figure 269. Example
903
Figure 270. MSB Justified 16-Bit or 32-Bit Full-Accuracy Length with CPOL = 0
904
Figure 271. MSB Justified 24-Bit Frame Length with CPOL = 0
904
Figure 272. MSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
904
Figure 273. LSB Justified 16-Bit or 32-Bit Full-Accuracy with CPOL = 0
905
Figure 274. LSB Justified 24-Bit Frame Length with CPOL = 0
905
Figure 275. Operations Required to Transmit 0X3478Ae
905
Figure 276. Operations Required to Receive 0X3478Ae
906
Figure 277. LSB Justified 16-Bit Extended to 32-Bit Packet Frame with CPOL = 0
906
Figure 278. Example of LSB Justified 16-Bit Extended to 32-Bit Packet Frame
906
Figure 279. PCM Standard Waveforms (16-Bit)
907
Figure 280. PCM Standard Waveforms (16-Bit Extended to 32-Bit Packet Frame)
907
Figure 281. Audio Sampling Frequency Definition
908
Figure 282. I
908
Table 127. Audio Frequency Precision (for PLLM VCO = 1 Mhz or 2 Mhz)
909
Table 128. I 2 S Interrupt Requests
915
Table 129. SPI Register Map and Reset Values
925
Figure 283. Functional Block Diagram
928
Figure 284. Audio Frame
930
Figure 285. FS Role Is Start of Frame + Channel Side Identification (FSDEF = TRIS = 1)
933
Figure 286. FS Role Is Start of Frame (FSDEF = 0)
933
Figure 287. Slot Size Configuration with FBOFF = 0 in Sai_Xslotr
934
Figure 288. First Bit Offset
934
Figure 289. Audio Block Clock Generator Overview
935
Table 130. Example of Possible Audio Frequency Sampling Range
936
Figure 290. AC'97 Audio Frame
939
Figure 291. Data Companding Hardware in an Audio Block in the SAI
941
Figure 292. Tristate Strategy on SD Output Line on an Inactive Slot
943
Figure 293. Tristate on Output Data Line in a Protocol Like I2S
944
Figure 294. Overrun Detection Error
945
Figure 295. FIFO Underrun Event
946
Table 131. Interrupt Sources
948
Table 132. SAI Register Map and Reset Values
963
Figure 296. USART Block Diagram
968
Figure 297. Word Length Programming
969
Figure 298. Configurable Stop Bits
971
Figure 299. TC/TXE Behavior When Transmitting
972
Figure 300. Start Bit Detection When Oversampling by 16 or 8
973
Figure 301. Data Sampling When Oversampling by 16
976
Figure 302. Data Sampling When Oversampling by 8
977
Table 133. Noise Detection from Sampled Data
977
Oversampling by 16
980
PCLK = 8 Mhz or F PCLK = 12 Mhz
980
Table 134. Error Calculation for Programmed Baud Rates at F
980
Oversampling by 16
981
Oversampling by 8
981
Oversampling by 8
982
Oversampling by 16
983
Oversampling by 8
983
Oversampling by 16
984
Oversampling by 8
985
Oversampling by 16
986
Oversampling by 8
987
Table 144. USART Receiver's Tolerance When DIV Fraction Is 0
988
Table 145. USART Receiver Tolerance When Div_Fraction Is Different from 0
989
Figure 303. Mute Mode Using Idle Line Detection
990
Figure 304. Mute Mode Using Address Mark Detection
990
Table 146. Frame Formats
991
Figure 305. Break Detection in LIN Mode (11-Bit Break Length - LBDL Bit Is Set)
993
Figure 306. Break Detection in LIN Mode Vs. Framing Error Detection
994
Figure 307. USART Example of Synchronous Transmission
995
Figure 308. USART Data Clock Timing Diagram (M=0)
995
Figure 309. USART Data Clock Timing Diagram (M=1)
996
Figure 310. RX Data Setup/Hold Time
996
Figure 311. ISO 7816-3 Asynchronous Protocol
997
Figure 312. Parity Error Detection Using the 1.5 Stop Bits
998
Figure 313. Irda SIR ENDEC- Block Diagram
1000
Figure 314. Irda Data Modulation (3/16) -Normal Mode
1000
Figure 315. Transmission Using DMA
1002
Figure 316. Reception Using DMA
1003
Figure 317. Hardware Flow Control between 2 Usarts
1003
Figure 318. RTS Flow Control
1004
Figure 319. CTS Flow Control
1005
Figure 320. USART Interrupt Mapping Diagram
1006
Table 147. USART Interrupt Requests
1006
Table 148. USART Mode Configuration
1007
Table 149. USART Register Map and Reset Values
1018
Figure 321. SDIO "No Response" and "No Data" Operations
1020
Figure 322. SDIO (Multiple) Block Read Operation
1020
Figure 323. SDIO (Multiple) Block Write Operation
1021
Figure 324. SDIO Sequential Read Operation
1021
Figure 325. SDIO Sequential Write Operation
1021
Figure 326. SDIO Block Diagram
1022
Figure 327. SDIO Adapter
1023
Table 150. SDIO I/O Definitions
1023
Figure 328. Control Unit
1024
Figure 329. SDIO Adapter Command Path
1025
Figure 330. Command Path State Machine (CPSM)
1026
Figure 331. SDIO Command Transfer
1027
Table 151. Command Format
1027
Table 152. Short Response Format
1028
Table 153. Long Response Format
1028
Table 154. Command Path Status Flags
1028
Figure 332. Data Path
1029
Figure 333. Data Path State Machine (DPSM)
1030
Table 155. Data Token Format
1031
Table 156. Transmit FIFO Status Flags
1032
Table 157. Receive FIFO Status Flags
1033
Table 158. Card Status
1043
Table 159. SD Status
1046
Table 160. Speed Class Code Field
1047
Table 161. Performance Move Field
1047
Table 162. AU_SIZE Field
1048
Table 163. Maximum au Size
1048
Table 164. Erase Size Field
1048
Table 165. Erase Timeout Field
1049
Table 166. Erase Offset Field
1049
Table 167. Block-Oriented Write Commands
1051
Table 168. Block-Oriented Write Protection Commands
1052
Table 169. Erase Commands
1052
Table 170. I/O Mode Commands
1053
Table 171. Lock Card
1053
Table 172. Application-Specific Commands
1053
Table 173. R1 Response
1054
Table 174. R2 Response
1055
Table 175. R3 Response
1055
Table 176. R4 Response
1055
Table 177. R4B Response
1056
Table 178. R5 Response
1056
Table 179. R6 Response
1057
Table 180. Response Type and Sdio_Respx Registers
1064
Table 181. SDIO Register Map
1074
Figure 334. CAN Network Topology
1077
Figure 335. Dual CAN Block Diagram
1079
Figure 336. Bxcan Operating Modes
1081
Figure 337. Bxcan in Silent Mode
1082
Figure 338. Bxcan in Loop Back Mode
1082
Figure 339. Bxcan in Combined Mode
1083
Figure 340. Transmit Mailbox States
1085
Figure 341. Receive FIFO States
1086
Figure 342. Filter Bank Scale Configuration - Register Organization
1088
Figure 343. Example of Filter Numbering
1089
Figure 344. Filtering Mechanism - Example
1090
Table 182. Transmit Mailbox Mapping
1091
Table 183. Receive Mailbox Mapping
1091
Figure 345. CAN Error State Diagram
1092
Figure 346. Bit Timing
1094
Figure 347. CAN Frames
1095
Figure 348. Event Flags and Interrupt Generation
1096
Figure 349. RX and TX Mailboxes
1107
Table 184. Bxcan Register Map and Reset Values
1118
Table 185. Alternate Function Mapping
1125
Figure 350. ETH Block Diagram
1126
Figure 351. SMI Interface Signals
1127
Table 186. Management Frame Format
1127
Figure 352. MDIO Timing and Frame Structure - Write Cycle
1128
Figure 353. MDIO Timing and Frame Structure - Read Cycle
1129
Figure 354. Media Independent Interface Signals
1129
Table 187. Clock Range
1129
Table 188. TX Interface Signal Encoding
1130
Figure 355. MII Clock Sources
1131
Table 189. RX Interface Signal Encoding
1131
Figure 356. Reduced Media-Independent Interface Signals
1132
Figure 357. RMII Clock Sources
1132
Figure 358. Clock Scheme
1133
Figure 359. Address Field Format
1135
Figure 360. MAC Frame Format
1136
Figure 361. Tagged MAC Frame Format
1137
Figure 362. Transmission Bit Order
1143
Figure 363. Transmission with no Collision
1143
Figure 364. Transmission with Collision
1144
Figure 365. Frame Transmission in MMI and RMII Modes
1144
Table 190. Frame Statuses
1146
Figure 366. Receive Bit Order
1148
Figure 367. Reception with no Error
1149
Figure 368. Reception with Errors
1149
Figure 369. Reception with False Carrier Indication
1149
Figure 370. MAC Core Interrupt Masking Scheme
1150
Table 191. Destination Address Filtering
1152
Table 192. Source Address Filtering
1153
Figure 371. Wakeup Frame Filter Register
1154
Figure 372. Networked Time Synchronization
1158
Figure 373. System Time Update Using the Fine Correction Method
1160
Figure 374. PTP Trigger Output to TIM2 ITR1 Connection
1162
Figure 375. PPS Output
1163
Figure 376. Descriptor Ring and Chain Structure
1164
Figure 377. Txdma Operation in Default Mode
1168
Figure 378. Txdma Operation in OSF Mode
1170
Figure 379. Normal Transmit Descriptor
1171
Figure 380. Enhanced Transmit Descriptor
1177
Figure 381. Receive DMA Operation
1179
Figure 382. Normal Rx DMA Descriptor Structure
1181
Table 193. Receive Descriptor 0 - Encoding for Bits 7, 5 and 0 (Normal Descriptor Format Only, EDFE=0)
1184
Figure 383. Enhanced Receive Descriptor Field Format with IEEE1588 Time Stamp Enabled
1187
Figure 384. Interrupt Scheme
1190
Figure 385. Ethernet MAC Remote Wakeup Frame Filter Register (ETH_MACRWUFFR)
1200
Table 194. Time Stamp Snapshot Dependency on Registers Bits
1217
Table 195. Ethernet Register Map and Reset Values
1236
Figure 386. OTG Full-Speed Block Diagram
1243
Table 196. OTG_FS Input/Output Pins
1243
Figure 387. OTG A-B Device Connection
1245
Figure 388. USB Peripheral-Only Connection
1247
Figure 389. USB Host-Only Connection
1251
Figure 390. SOF Connectivity
1255
Table 197. Compatibility of STM32 Low Power Modes with the OTG
1256
Figure 391. Updating OTG_FS_HFIR Dynamically
1258
Figure 392. Device-Mode FIFO Address Mapping and AHB FIFO Access Mapping
1259
Figure 393. Host-Mode FIFO Address Mapping and AHB FIFO Access Mapping
1260
Figure 394. Interrupt Hierarchy
1264
Figure 395. CSR Memory Map
1266
Table 198. Core Global Control and Status Registers (Csrs)
1266
Table 199. Host-Mode Control and Status Registers (Csrs)
1267
Table 200. Device-Mode Control and Status Registers
1268
Table 201. Data FIFO (DFIFO) Access Register Map
1269
Table 202. Power and Clock Gating Control and Status Registers
1270
Table 203. TRDT Values
1276
Table 204. Minimum Duration for Soft Disconnect
1304
Table 205. OTG_FS Register Map and Reset Values
1326
Figure 396. Transmit FIFO Write Task
1338
Figure 397. Receive FIFO Read Task
1339
Figure 398. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions
1340
Figure 399. Bulk/Control in Transactions
1343
Figure 400. Normal Interrupt OUT/IN Transactions
1345
Figure 401. Normal Isochronous OUT/IN Transactions
1350
Figure 402. Receive FIFO Packet Read
1356
Figure 403. Processing a SETUP Packet
1358
Figure 404. Bulk out Transaction
1365
Figure 405. TRDT Max Timing Case
1374
Figure 406. A-Device SRP
1375
Figure 407. B-Device SRP
1376
Figure 408. A-Device HNP
1377
Figure 409. B-Device HNP
1379
Figure 410. USB OTG Interface Block Diagram
1384
Table 206. OTG_HS Input/Output Pins
1384
Figure 411. USB Host-Only Connection
1391
Figure 412. SOF Trigger Output to TIM2 ITR1 Connection
1396
Table 207. Compatibility of STM32 Low Power Modes with the OTG
1397
Figure 413. Updating OTG_HS_HFIR Dynamically
1398
Figure 414. Interrupt Hierarchy
1401
Figure 415. CSR Memory Map
1403
Table 208. Core Global Control and Status Registers (Csrs)
1403
Table 209. Host-Mode Control and Status Registers (Csrs)
1404
Table 210. Device-Mode Control and Status Registers
1405
Table 211. Data FIFO (DFIFO) Access Register Map
1407
Table 212. Power and Clock Gating Control and Status Registers
1407
Table 213. TRDT Values
1414
Table 214. Minimum Duration for Soft Disconnect
1446
Table 215. OTG_HS Register Map and Reset Values
1472
Figure 416. Transmit FIFO Write Task
1492
Figure 417. Receive FIFO Read Task
1493
Figure 418. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions - DMA
1494
Mode
1494
Figure 419. Normal Bulk/Control OUT/SETUP and Bulk/Control in Transactions - Slave
1495
Mode
1495
Figure 420. Bulk/Control in Transactions - DMA Mode
1498
Figure 421. Bulk/Control in Transactions - Slave Mode
1499
Figure 422. Normal Interrupt OUT/IN Transactions - DMA Mode
1501
Figure 423. Normal Interrupt OUT/IN Transactions - Slave Mode
1502
Figure 424. Normal Isochronous OUT/IN Transactions - DMA Mode
1507
Figure 425. Normal Isochronous OUT/IN Transactions - Slave Mode
1508
Figure 426. Receive FIFO Packet Read in Slave Mode
1519
Figure 427. Processing a SETUP Packet
1521
Figure 428. Slave Mode Bulk out Transaction
1528
Figure 429. TRDT Max Timing Case
1537
Figure 430. A-Device SRP
1538
Figure 431. B-Device SRP
1539
Figure 432. A-Device HNP
1540
Figure 433. B-Device HNP
1542
Figure 434. FSMC Block Diagram
1545
Figure 435. FSMC Memory Banks
1547
Table 216. NOR/PSRAM Bank Selection
1548
Table 217. External Memory Address
1548
Table 218. Memory Mapping and Timing Registers
1548
Table 219. NAND Bank Selections
1549
Table 220. Programmable NOR/PSRAM Access Parameters
1550
Table 221. Nonmultiplexed I/O nor Flash
1550
Table 222. Multiplexed I/O nor Flash
1551
Table 223. Nonmultiplexed I/Os PSRAM/SRAM
1551
Table 224. Multiplexed I/O PSRAM
1552
Table 225. nor Flash/Psram Controller: Example of Supported Memories and Transactions
1552
Figure 436. Mode1 Read Accesses
1554
Figure 437. Mode1 Write Accesses
1555
Table 226. Fsmc_Bcrx Bit Fields
1555
Figure 438. Modea Read Accesses
1556
Table 227. Fsmc_Btrx Bit Fields
1556
Figure 439. Modea Write Accesses
1557
Table 228. Fsmc_Bcrx Bit Fields
1557
Table 229. Fsmc_Btrx Bit Fields
1558
Table 230. Fsmc_Bwtrx Bit Fields
1558
Figure 440. Mode2 and Mode B Read Accesses
1559
Figure 441. Mode2 Write Accesses
1559
Figure 442. Mode B Write Accesses
1560
Table 231. Fsmc_Bcrx Bit Fields
1560
Table 232. Fsmc_Btrx Bit Fields
1561
Table 233. Fsmc_Bwtrx Bit Fields
1561
Figure 443. Mode C Read Accesses
1562
Figure 444. Mode C Write Accesses
1562
Table 234. Fsmc_Bcrx Bit Fields
1563
Table 235. Fsmc_Btrx Bit Fields
1563
Figure 445. Mode D Read Accesses
1564
Table 236. Fsmc_Bwtrx Bit Fields
1564
Figure 446. Mode D Write Accesses
1565
Table 237. Fsmc_Bcrx Bit Fields
1565
Table 238. Fsmc_Btrx Bit Fields
1566
Table 239. Fsmc_Bwtrx Bit Fields
1566
Figure 447. Multiplexed Read Accesses
1567
Figure 448. Multiplexed Write Accesses
1567
Table 240. Fsmc_Bcrx Bit Fields
1568
Table 241. Fsmc_Btrx Bit Fields
1568
Figure 449. Asynchronous Wait During a Read Access
1570
Figure 450. Asynchronous Wait During a Write Access
1570
Figure 451. Wait Configurations
1572
Figure 452. Synchronous Multiplexed Read Mode - NOR, PSRAM (CRAM)
1573
Table 242. Fsmc_Bcrx Bit Fields
1573
Table 243. Fsmc_Btrx Bit Fields
1574
Figure 453. Synchronous Multiplexed Write Mode - PSRAM (CRAM)
1575
Table 244. Fsmc_Bcrx Bit Fields
1575
Table 245. Fsmc_Btrx Bit Fields
1576
Table 246. Programmable NAND/PC Card Access Parameters
1585
Table 247. 8-Bit NAND Flash
1585
Table 248. 16-Bit NAND Flash
1586
Table 249. 16-Bit PC Card
1586
Table 250. Supported Memories and Transactions
1587
Figure 454. NAND/PC Card Controller Timing for Common Memory Access
1588
Figure 455. Access to Non 'CE Don't Care' NAND-Flash
1589
Table 251. 16-Bit PC-Card Signals and Access Type
1592
Table 252. ECC Result Relevant Bits
1599
Table 253. FSMC Register Map
1600
Figure 456. FMC Block Diagram
1604
Figure 457. FMC Memory Banks
1607
Table 254. NOR/PSRAM Bank Selection
1607
Table 255. NOR/PSRAM External Memory Address
1608
Table 256. NAND/PC Card Memory Mapping and Timing Registers
1608
Table 257. NAND Bank Selection
1609
Table 258. SDRAM Bank Selection
1609
Table 259. SDRAM Address Mapping
1609
Table 260. SDRAM Address Mapping with 8-Bit Data Bus Width
1610
Table 261. SDRAM Address Mapping with 16-Bit Data Bus Width
1611
Table 262. SDRAM Address Mapping with 32-Bit Data Bus Width
1611
Table 263. Programmable NOR/PSRAM Access Parameters
1613
Table 264. Non-Multiplexed I/O nor Flash Memory
1614
Table 265. 16-Bit Multiplexed I/O nor Flash Memory
1614
Table 266. Non-Multiplexed I/Os PSRAM/SRAM
1614
Table 267. 16-Bit Multiplexed I/O PSRAM
1615
Table 268. nor Flash/Psram: Example of Supported Memories and Transactions
1616
Figure 458. Mode1 Read Access Waveforms
1618
Figure 459. Mode1 Write Access Waveforms
1618
Table 269. Fmc_Bcrx Bit Fields
1619
Table 270. Fmc_Btrx Bit Fields
1619
Figure 460. Modea Read Access Waveforms
1620
Figure 461. Modea Write Access Waveforms
1621
Table 271. Fmc_Bcrx Bit Fields
1621
Table 272. Fmc_Btrx Bit Fields
1622
Table 273. Fmc_Bwtrx Bit Fields
1622
Figure 462. Mode2 and Mode B Read Access Waveforms
1623
Figure 463. Mode2 Write Access Waveforms
1623
Figure 464. Modeb Write Access Waveforms
1624
Table 274. Fmc_Bcrx Bit Fields
1624
Table 275. Fmc_Btrx Bit Fields
1625
Table 276. Fmc_Bwtrx Bit Fields
1625
Figure 465. Modec Read Access Waveforms
1626
Figure 466. Modec Write Access Waveforms
1626
Table 277. Fmc_Bcrx Bit Fields
1627
Table 278. Fmc_Btrx Bit Fields
1627
Figure 467. Moded Read Access Waveforms
1628
Table 279. Fmc_Bwtrx Bit Fields
1628
Figure 468. Moded Write Access Waveforms
1629
Table 280. Fmc_Bcrx Bit Fields
1629
Table 281. Fmc_Btrx Bit Fields
1630
Table 282. Fmc_Bwtrx Bit Fields
1630
Figure 469. Muxed Read Access Waveforms
1631
Figure 470. Muxed Write Access Waveforms
1631
Table 283. Fmc_Bcrx Bit Fields
1632
Table 284. Fmc_Btrx Bit Fields
1632
Figure 471. Asynchronous Wait During a Read Access Waveforms
1633
Figure 472. Asynchronous Wait During a Write Access Waveforms
1634
Figure 473. Wait Configuration Waveforms
1636
Figure 474. Synchronous Multiplexed Read Mode Waveforms - NOR, PSRAM (CRAM)
1636
Table 285. Fmc_Bcrx Bit Fields
1637
Table 286. Fmc_Btrx Bit Fields
1637
Figure 475. Synchronous Multiplexed Write Mode Waveforms - PSRAM (CRAM)
1638
Table 287. Fmc_Bcrx Bit Fields
1638
Table 288. Fmc_Btrx Bit Fields
1639
Table 289. Programmable NAND Flash/Pc Card Access Parameters
1648
Table 290. 8-Bit NAND Flash
1648
Table 291. 16-Bit NAND Flash
1649
Table 292. 16-Bit PC Card
1649
Table 293. Supported Memories and Transactions
1650
Figure 476. NAND Flash/Pc Card Controller Waveforms for Common Memory Access
1651
Figure 477. Access to Non 'CE Don't Care' NAND-Flash
1652
Table 294. 16-Bit PC-Card Signals and Access Type
1655
Table 295. ECC Result Relevant Bits
1662
Table 296. SDRAM Signals
1663
Figure 478. Burst Write SDRAM Access Waveforms
1665
Figure 479. Burst Read SDRAM Access
1666
Figure 480. Logic Diagram of Read Access with RBURST Bit Set (CAS=2, RPIPE=0)
1667
Figure 481. Read Access Crossing Row Boundary
1669
Figure 482. Write Access Crossing Row Boundary
1669
Figure 483. Self-Refresh Mode
1672
Figure 484. Power-Down Mode
1673
Table 297. FMC Register Map
1680
Figure 485. Block Diagram of STM32 MCU and Cortex
1683
Figure 486. SWJ Debug Port
1685
Table 298. SWJ Debug Port Pins
1686
Table 299. Flexible SWJ-DP Pin Assignment
1686
Figure 487. JTAG TAP Connections
1689
Table 300. JTAG Debug Port Data Registers
1691
Table 301. 32-Bit Debug Port Registers Addressed through the Shifted Value A[3:2]
1692
Table 302. Packet Request (8-Bits)
1693
Table 303. ACK Response (3 Bits)
1694
Table 304. DATA Transfer (33 Bits)
1694
Table 305. SW-DP Registers
1695
Table 306. Cortex ® -M4 with FPU AHB-AP Registers
1696
Table 307. Core Debug Registers
1697
Table 308. Main ITM Registers
1700
Table 309. Main ETM Registers
1702
Figure 488. TPIU Block Diagram
1707
Table 310. Asynchronous TRACE Pin Assignment
1708
Table 311. Synchronous TRACE Pin Assignment
1708
Table 312. Flexible TRACE Pin Assignment
1709
Table 313. Important TPIU Registers
1711
Table 314. DBG Register Map and Reset Values
1713
Table 315. Document Revision History
1716
Table 143. Error Calculation for Programmed Baud Rates at Fpclk = 42 Mhz or Fpclk = 84 Mhz
1719
Table 142. Error Calculation for Programmed Baud Rates at Fpclk = 42 Mhz or Fpclk = 84 Hz
1742
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ST STM32F405 Specifications
General
Brand
ST
Model
STM32F405
Category
Computer Hardware
Language
English
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