Universal synchronous asynchronous receiver transmitter (USART) RM0090
1006/1749 RM0090 Rev 18
30.4 USART interrupts
The USART interrupt events are connected to the same interrupt vector (see Figure 320).
• During transmission: Transmission Complete, Clear to Send or Transmit Data Register
empty interrupt.
• While receiving: Idle Line detection, Overrun error, Receive Data register not empty,
Parity error, LIN break detection, Noise Flag (only in multi buffer communication) and
Framing Error (only in multi buffer communication).
These events generate an interrupt if the corresponding Enable Control Bit is set.
Figure 320. USART interrupt mapping diagram
Table 147. USART interrupt requests
Interrupt event Event flag
Enable control
bit
Transmit Data Register Empty TXE TXEIE
CTS flag CTS CTSIE
Transmission Complete TC TCIE
Received Data Ready to be Read RXNE
RXNEIE
Overrun Error Detected ORE
Idle Line Detected IDLE IDLEIE
Parity Error PE PEIE
Break Flag LBD LBDIE
Noise Flag, Overrun error and Framing Error in multibuffer
communication
NF or ORE or FE EIE
MSv42089V1
TC
TCIE
TXE
TXEIE
CTSIF
CTSIE
IDLE
IDLEIE
RXNEIE
ORE
RXNEIE
RXNE
PE
PEIE
LBD
LBDIE
FE
NE
ORE
EIE
USART
interrupt
DMAR
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