ST STM32F405 User Manual

RM0090 Rev 18 1683/1749
RM0090 Debug support (DBG)
1713
38 Debug support (DBG)
This section applies to the whole STM32F4xx family, unless otherwise specified.
38.1 Overview
The STM32F4xx are built around a Cortex
®
-M4 with FPU core which contains hardware
extensions for advanced debugging features. The debug extensions allow the core to be
stopped either on a given instruction fetch (breakpoint) or data access (watchpoint). When
stopped, the core’s internal state and the system’s external state may be examined. Once
examination is complete, the core and the system may be restored and program execution
resumed.
The debug features are used by the debugger host when connecting to and debugging the
STM32F4xx MCUs.
Two interfaces for debug are available:
• Serial wire
• JTAG debug port
Figure 485. Block diagram of STM32 MCU and Cortex
®
-M4 with FPU-level debug
support
Note: The debug features embedded in the Cortex
®
-M4 with FPU core are a subset of the Arm
®
CoreSight Design Kit.
e
s
t
r
i
c
t
e
d
D
i
Cortex-M4
core
SWJ-DP
AHB-AP
Bridge
NVIC
DWT
FPB
ITM
TPIU
DCode
interface
System
interface
Internal private
peripheral bus (PPB)
External private
peripheral bus (PPB)
Bus matrix
Data
Trace po r t
DBGMCU
STM32F4xx debug support
Cortex-M4 debug s uppo rt
JTMS/
JTDI
JTDO/
NJTRST
JTCK/
SWDIO
SWCLK
TRACESWO
TRACESWO
TRACECK
TRACED[3:0]
MS19908V3

ST STM32F405 Specifications

General

Brand	ST
Model	STM32F405
Category	Computer Hardware
Language	English