Flexible static memory controller (FSMC) RM0090
1568/1749 RM0090 Rev 18
WAIT management in asynchronous accesses
If the asynchronous memory asserts a WAIT signal to indicate that it is not yet ready to
accept or to provide data, the ASYNCWAIT bit has to be set in FSMC_BCRx register.
Table 240. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-21 Reserved 0x000
19 CBURSTRW 0x0 (no effect on asynchronous mode)
18:16 CPSIZE 0x0 (no effect on asynchronous mode)
15 ASYNCWAIT
Set to 1 if the memory supports this feature. Otherwise keep at
0.
14 EXTMOD 0x0
13 WAITEN 0x0 (no effect on asynchronous mode)
12 WREN As needed
11 WAITCFG Don’t care
10 WRAPMOD 0x0
9 WAITPOL Meaningful only if bit 15 is 1
8 BURSTEN 0x0
7 Reserved 0x1
6 FACCEN 0x1
5-4 MWID As needed
3-2 MTYP[0:1] 0x2 (NOR Flash memory)
1 MUXEN 0x1
0 MBKEN 0x1
Table 241. FSMC_BTRx bit fields
Bit No. Bit name Value to set
31:30 Reserved 0x0
29-28 ACCMOD 0x0
27-24 DATLAT Don’t care
23-20 CLKDIV Don’t care
19-16 BUSTURN Time between NEx high to NEx low (BUSTURN HCLK)
15-8 DATAST
Duration of the second access phase (DATAST HCLK cycles for
read accesses and DATAST+1 HCLK cycles for write accesses).
7-4 ADDHLD Duration of the middle phase of the access (ADDHLD HCLK cycles).
3-0 ADDSET[3:0]
Duration of the first access phase (ADDSET HCLK cycles).
Minimum value for ADDSET is 1.
To Next Page
Loading...
Need help?
General
