ST STM32F405

RM0090 Rev 18 1567/1749
RM0090 Flexible static memory controller (FSMC)
1601
Muxed mode - multiplexed asynchronous access to NOR Flash memory
Figure 447. Multiplexed read accesses
Figure 448. Multiplexed write accesses
The difference with mode D is the drive of the lower address byte(s) on the databus.
A[25:16]
NOE
ADDSET (DATAST + 1)
Memory transaction
NEx
AD[15:0]
HCLK cycles HCLK cycles
NWE
NADV
data driven by FSMC
ai15569
1HCLK
ADDHLD
HCLK cycles
Lower address