ST STM32F405

RM0090 Rev 18 1573/1749
RM0090 Flexible static memory controller (FSMC)
1601
Figure 452. Synchronous multiplexed read mode - NOR, PSRAM (CRAM)
1. Byte lane outputs BL are not shown; for NOR access, they are held high, and, for PSRAM (CRAM) access,
they are held low.
2. NWAIT polarity is set to 0.
Table 242. FSMC_BCRx bit fields
Bit No. Bit name Value to set
31-20 Reserved 0x000
19 CBURSTRW No effect on synchronous read
18-16 CPSIZE As needed (0x1 for CRAM 1.5)
15 ASCYCWAIT 0x0
14 EXTMOD 0x0
13 WAITEN Set to 1 if the memory supports this feature, otherwise keep at 0.
12 WREN no effect on synchronous read
11 WAITCFG to be set according to memory
10 WRAPMOD 0x0
9 WAITPOL to be set according to memory
8 BURSTEN 0x1
7 Reserved 0x1
6 FACCEN Set according to memory support (NOR Flash memory)
5-4 MWID As needed
Addr[15:0] data data
addr[25:16]
Memory transaction = burst of 4 half words
HCLK
CLK
A[25:16]
NEx
NOE
NWE
High
NADV
NWAIT
(WAITCFG=
0)
A/D[15:0]
1 clock
cycle
1 clock
cycle
(DATLAT + 2)
inserted wait state
Data strobes
ai17723f
CLK cycles
data data
Data strobes