RM0090 Rev 18 941/1749
RM0090 Serial audio interface (SAI)
964
with a distinct and different left and right data, bit MONO has no meaning. The conversion
from the output stereo file to the equivalent mono file is done by software.
Note: To enable Mono mode, NBSLOT and SLOTEN must equal two and MONO bit set to 1.
29.12.3 Companding mode
Telecommunication applications may require to process the data to transmit or to receive
with a data companding algorithm.
Depending on the COMP[1:0] bit in the SAI_xCR2 register (used only when TDM mode is
selected), the software may choose to process or not the data before sending it on SD serial
output line (compression) or to expand the data after the reception on SD serial input line
(expansion) as illustrated in Figure 291,.The two companding modes supported are the µ-
Law and the A-Law log which are a part of the CCITT G.711 recommendation.
The companding standard employed in the United States and Japan is the µ-Law and allows
14 bits of dynamic range (COMP[1:0] = 10 in the SAI_xCR2 register).
The European companding standard is A-Law and allows 13 bits of dynamic range
(COMP[1:0] = 11 in the SAI_xCR2 register).
Companding standard (µ-Law or A-Law) can be computed based on 1’s complement or 2’s
complement representation depending on the CPL bit setting in the SAI_xCR2 register.
The µ-Law and A-Law formats encode data into 8-bit code elements with MSB alignment.
Companded data is always 8 bits wide. For this reason, bit DS[2:0] in the SAI_xCR1 register
will be forced to 010 when the SAI audio block is enabled (bit SAIxEN = 1 in the SAI_xCR1
register) and when the COMP[1:0] bit selects one of these two companding modes.
If no companding processing is required, COMP[1:0] bit in the SAI_xCR2 register should be
kept cleared.
Figure 291. Data companding hardware in an audio block in the SAI
Note: Not applicable when AC’97 selected.
expand
FIFO
COMP[1]
COMP[1]
32-bit shift register
SD
Receiver mode (bit MODE[0] = 1 in SAI_xCR1)
Transmitter mode (bit MODE[0] = 0 in SAI_xCR1)
MS19244V1
1
0
1
0
32-bit shift register
SD
compress
FIFO
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