Flexible static memory controller (FSMC) RM0090
1572/1749 RM0090 Rev 18
If NWAIT is sensed active (low level when WAITPOL = 0, high level when WAITPOL = 1),
wait states are inserted until NWAIT is sensed inactive (high level when WAITPOL = 0, low
level when WAITPOL = 1).
When NWAIT is inactive, the data is considered valid either immediately (bit WAITCFG = 1)
or on the next clock edge (bit WAITCFG = 0).
During wait-state insertion via the NWAIT signal, the controller continues to send clock
pulses to the memory, keeping the chip select and output enable signals valid, and does not
consider the data valid.
There are two timing configurations for the NOR Flash NWAIT signal in burst mode:
• Flash memory asserts the NWAIT signal one data cycle before the wait state (default
after reset)
• Flash memory asserts the NWAIT signal during the wait state
These two NOR Flash wait state configurations are supported by the FSMC, individually for
each chip select, thanks to the WAITCFG bit in the FSMC_BCRx registers (x = 0..3).
Figure 451. Wait configurations
aaddr[15:0] data data
addr[25:16]
Memory transaction = burst of 4 half words
HCLK
CLK
A[25:16]
NADV
NWAIT
(WAITCFG = 1)
A/D[15:0]
inserted wait state
data
NWAIT
(WAITCFG = 0)
ai15798b
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