RM0090 Rev 18 1143/1749
RM0090 Ethernet (ETH): media access control (MAC) with DMA controller
1239
UDP or ICMP header is not modified. For the second error type, still, the calculated
checksum is inserted into the corresponding header field.
MII/RMII transmit bit order
Each nibble from the MII is transmitted on the RMII a dibit at a time with the order of dibit
transmission shown in Figure 362. Lower order bits (D1 and D0) are transmitted first
followed by higher order bits (D2 and D3).
Figure 362. Transmission bit order
MII/RMII transmit timing diagrams
Figure 363. Transmission with no collision
D0
D1
D2
D3
LSB
MII_TXD[3:0]
MSB
D0 D1
LSB MSB
RMII_TXD[1:0]
Bibit stream
Nibble stream
ai15632
MII_TX_CLK
MII_TX_EN
MII_TXD[3:0]
PR EA MB LE
MII_CS
MII_COL
ai1563
Low
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